diff --git a/artiq/coredevice/dds.py b/artiq/coredevice/dds.py
index 527c6d9ee..691500337 100644
--- a/artiq/coredevice/dds.py
+++ b/artiq/coredevice/dds.py
@@ -26,6 +26,7 @@ class DDS(AutoContext):
     parameters = "dds_sysclk reg_channel rtio_switch"
 
     def build(self):
+        self.previous_on = False
         self.previous_frequency = 0*MHz
         self.set_phase_mode(PHASE_MODE_CONTINUOUS)
         self.sw = rtio.RTIOOut(self, channel=self.rtio_switch)
@@ -95,7 +96,7 @@ class DDS(AutoContext):
             # Channel is off:
             # Use soft timing on FUD to prevent conflicts when reprogramming
             # several channels that need to be turned on at the same time.
-            rt_fud = merge or bool(self.sw.previous_value)
+            rt_fud = merge or self.previous_on
             ftw = self.frequency_to_ftw(frequency)
             if self.phase_mode != PHASE_MODE_CONTINUOUS:
                 phase_per_microcycle = ftw*int64(
@@ -108,6 +109,7 @@ class DDS(AutoContext):
                rt_fud, self.phase_mode == PHASE_MODE_TRACKING)
             self.previous_frequency = frequency
         self.sw.on()
+        self.previous_on = True
 
         if phase_mode != PHASE_MODE_DEFAULT:
             self.set_phase_mode(old_phase_mode)
@@ -118,6 +120,7 @@ class DDS(AutoContext):
 
         """
         self.sw.off()
+        self.previous_on = False
 
     @kernel
     def pulse(self, frequency, duration,
diff --git a/artiq/coredevice/rtio.py b/artiq/coredevice/rtio.py
index c95297cd6..279fff996 100644
--- a/artiq/coredevice/rtio.py
+++ b/artiq/coredevice/rtio.py
@@ -14,7 +14,6 @@ class LLRTIOOut(AutoContext):
     parameters = "channel"
 
     def build(self):
-        self.previous_timestamp = int64(0)  # in RTIO cycles
         self._set_oe()
 
     @kernel
@@ -30,7 +29,6 @@ class LLRTIOOut(AutoContext):
 
         """
         syscall("rtio_set", t, self.channel, value)
-        self.previous_timestamp = t
 
     @kernel
     def on(self, t):
@@ -56,7 +54,6 @@ class _RTIOBase(AutoContext):
 
     def build(self):
         self.previous_timestamp = int64(0)  # in RTIO cycles
-        self.previous_value = 0
 
     @kernel
     def _set_oe(self, oe):
@@ -66,7 +63,6 @@ class _RTIOBase(AutoContext):
     def _set_value(self, value):
         syscall("rtio_set", time_to_cycles(now()), self.channel, value)
         self.previous_timestamp = time_to_cycles(now())
-        self.previous_value = value
 
 
 class RTIOOut(_RTIOBase):