diff --git a/artiq/gateware/drtio/rt_controller_master.py b/artiq/gateware/drtio/rt_controller_master.py
index d9186a498..e8cd241ca 100644
--- a/artiq/gateware/drtio/rt_controller_master.py
+++ b/artiq/gateware/drtio/rt_controller_master.py
@@ -230,6 +230,7 @@ class RTController(Module):
         )
         fsm.act("READ",
             i_status_wait_status.eq(1),
+            rt_packet.read_not_ack.eq(1),
             rt_packet_read_request.eq(1),
             rt_packet.sr_stb.eq(1),
             If(rt_packet.sr_ack,
@@ -238,6 +239,7 @@ class RTController(Module):
         )
         fsm.act("GET_READ_REPLY",
             i_status_wait_status.eq(1),
+            rt_packet.read_not_ack.eq(1),
             If(rt_packet.read_not,
                 load_read_reply.eq(1),
                 NextState("IDLE")
diff --git a/artiq/gateware/drtio/rt_ios_satellite.py b/artiq/gateware/drtio/rt_ios_satellite.py
index 71d430f95..55a0652e1 100644
--- a/artiq/gateware/drtio/rt_ios_satellite.py
+++ b/artiq/gateware/drtio/rt_ios_satellite.py
@@ -106,6 +106,8 @@ class IOS(Module):
             self.sync.rio += interface.fine_ts.eq(fifo_out.timestamp[:fine_ts_width])
 
     def add_input(self, n, channel):
+        rt_packet = self.rt_packet
+
         interface = channel.interface.i
         if interface is None:
             return