mirror of https://github.com/m-labs/artiq.git
ad9910 osk (#1387)
* updated adoo10.py for RAM mode frequency control * updated docstrings for set_cfr1() in ad9910.py * fixed typo in ad9910.py * added docstrings to ad9910.py * removed OSK-related changes in AD9910, to be included in a separate branch. * updated AD9910 set_cfr1 for control of OSK mode parameters * updated AD9910 set_cfr1() for control of OSK mode parameters.
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@ -345,7 +345,8 @@ class AD9910:
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@kernel
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@kernel
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def set_cfr1(self, power_down=0b0000, phase_autoclear=0,
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def set_cfr1(self, power_down=0b0000, phase_autoclear=0,
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drg_load_lrr=0, drg_autoclear=0,
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drg_load_lrr=0, drg_autoclear=0,
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internal_profile=0, ram_destination=0, ram_enable=0):
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internal_profile=0, ram_destination=0, ram_enable=0,
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manual_osk_external=0, osk_enable=0, select_auto_osk=0):
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"""Set CFR1. See the AD9910 datasheet for parameter meanings.
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"""Set CFR1. See the AD9910 datasheet for parameter meanings.
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This method does not pulse IO_UPDATE.
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This method does not pulse IO_UPDATE.
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@ -359,14 +360,20 @@ class AD9910:
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(:const:`RAM_DEST_FTW`, :const:`RAM_DEST_POW`,
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(:const:`RAM_DEST_FTW`, :const:`RAM_DEST_POW`,
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:const:`RAM_DEST_ASF`, :const:`RAM_DEST_POWASF`).
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:const:`RAM_DEST_ASF`, :const:`RAM_DEST_POWASF`).
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:param ram_enable: RAM mode enable.
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:param ram_enable: RAM mode enable.
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:param manual_osk_external: Enable OSK pin control in manual OSK mode.
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:param osk_enable: Enable OSK mode.
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:param select_auto_osk: Select manual or automatic OSK mode.
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"""
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"""
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self.write32(_AD9910_REG_CFR1,
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self.write32(_AD9910_REG_CFR1,
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(ram_enable << 31) |
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(ram_enable << 31) |
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(ram_destination << 29) |
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(ram_destination << 29) |
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(manual_osk_external << 23) |
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(internal_profile << 17) |
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(internal_profile << 17) |
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(drg_load_lrr << 15) |
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(drg_load_lrr << 15) |
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(drg_autoclear << 14) |
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(drg_autoclear << 14) |
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(phase_autoclear << 13) |
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(phase_autoclear << 13) |
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(osk_enable << 9) |
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(select_auto_osk << 8) |
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(power_down << 4) |
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(power_down << 4) |
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2) # SDIO input only, MSB first
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2) # SDIO input only, MSB first
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