mirror of https://github.com/m-labs/artiq.git
gateware.spi: rewrite counter bias for timing
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9a1d6a51a4
commit
5480099f1b
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@ -13,14 +13,21 @@ class SPIClockGen(Module):
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self.clk = Signal(reset=1)
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self.clk = Signal(reset=1)
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cnt = Signal.like(self.load)
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cnt = Signal.like(self.load)
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bias = Signal()
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zero = Signal()
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self.comb += [
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self.comb += [
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self.edge.eq(cnt == 0),
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zero.eq(cnt == 0),
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self.edge.eq(zero & ~bias),
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]
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]
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self.sync += [
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self.sync += [
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cnt.eq(cnt - 1),
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If(zero,
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bias.eq(0),
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).Else(
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cnt.eq(cnt - 1),
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),
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If(self.edge,
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If(self.edge,
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cnt.eq(self.load[1:] +
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cnt.eq(self.load[1:]),
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(self.load[0] & (self.clk ^ self.bias))),
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bias.eq(self.load[0] & (self.clk ^ self.bias)),
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self.clk.eq(~self.clk),
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self.clk.eq(~self.clk),
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)
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)
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]
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]
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