From 5480099f1bbddb848c389d7a0395973ed6469013 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Mon, 29 Feb 2016 02:28:19 +0100 Subject: [PATCH] gateware.spi: rewrite counter bias for timing --- artiq/gateware/spi.py | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/artiq/gateware/spi.py b/artiq/gateware/spi.py index 8a758d003..dabb89a40 100644 --- a/artiq/gateware/spi.py +++ b/artiq/gateware/spi.py @@ -13,14 +13,21 @@ class SPIClockGen(Module): self.clk = Signal(reset=1) cnt = Signal.like(self.load) + bias = Signal() + zero = Signal() self.comb += [ - self.edge.eq(cnt == 0), + zero.eq(cnt == 0), + self.edge.eq(zero & ~bias), ] self.sync += [ - cnt.eq(cnt - 1), + If(zero, + bias.eq(0), + ).Else( + cnt.eq(cnt - 1), + ), If(self.edge, - cnt.eq(self.load[1:] + - (self.load[0] & (self.clk ^ self.bias))), + cnt.eq(self.load[1:]), + bias.eq(self.load[0] & (self.clk ^ self.bias)), self.clk.eq(~self.clk), ) ]