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eem_7series: pass through kwargs
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49299c00a9
commit
547254e89e
@ -2,7 +2,7 @@ from artiq.gateware import eem
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, edge_counter
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, edge_counter
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def peripheral_dio(module, peripheral):
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def peripheral_dio(module, peripheral, **kwargs):
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ttl_classes = {
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ttl_classes = {
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"input": ttl_serdes_7series.InOut_8X,
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"input": ttl_serdes_7series.InOut_8X,
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"output": ttl_serdes_7series.Output_8X
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"output": ttl_serdes_7series.Output_8X
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@ -16,10 +16,10 @@ def peripheral_dio(module, peripheral):
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eem.DIO.add_std(module, peripheral["ports"][0],
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eem.DIO.add_std(module, peripheral["ports"][0],
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ttl_classes[peripheral["bank_direction_low"]],
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ttl_classes[peripheral["bank_direction_low"]],
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ttl_classes[peripheral["bank_direction_high"]],
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ttl_classes[peripheral["bank_direction_high"]],
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edge_counter_cls=edge_counter_cls)
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edge_counter_cls=edge_counter_cls, **kwargs)
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def peripheral_urukul(module, peripheral):
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def peripheral_urukul(module, peripheral, **kwargs):
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if len(peripheral["ports"]) == 1:
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if len(peripheral["ports"]) == 1:
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port, port_aux = peripheral["ports"][0], None
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port, port_aux = peripheral["ports"][0], None
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elif len(peripheral["ports"]) == 2:
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elif len(peripheral["ports"]) == 2:
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@ -31,26 +31,28 @@ def peripheral_urukul(module, peripheral):
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else:
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else:
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sync_gen_cls = None
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sync_gen_cls = None
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eem.Urukul.add_std(module, port, port_aux, ttl_serdes_7series.Output_8X,
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eem.Urukul.add_std(module, port, port_aux, ttl_serdes_7series.Output_8X,
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sync_gen_cls)
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sync_gen_cls, **kwargs)
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def peripheral_novogorny(module, peripheral):
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def peripheral_novogorny(module, peripheral, **kwargs):
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if len(peripheral["ports"]) != 1:
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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raise ValueError("wrong number of ports")
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eem.Novogorny.add_std(module, peripheral["ports"][0], ttl_serdes_7series.Output_8X)
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eem.Novogorny.add_std(module, peripheral["ports"][0],
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ttl_serdes_7series.Output_8X, **kwargs)
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def peripheral_sampler(module, peripheral):
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def peripheral_sampler(module, peripheral, **kwargs):
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if len(peripheral["ports"]) == 1:
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if len(peripheral["ports"]) == 1:
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port, port_aux = peripheral["ports"][0], None
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port, port_aux = peripheral["ports"][0], None
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elif len(peripheral["ports"]) == 2:
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elif len(peripheral["ports"]) == 2:
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port, port_aux = peripheral["ports"]
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port, port_aux = peripheral["ports"]
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else:
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else:
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raise ValueError("wrong number of ports")
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raise ValueError("wrong number of ports")
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eem.Sampler.add_std(module, port, port_aux, ttl_serdes_7series.Output_8X)
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eem.Sampler.add_std(module, port, port_aux, ttl_serdes_7series.Output_8X,
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**kwargs)
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def peripheral_suservo(module, peripheral):
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def peripheral_suservo(module, peripheral, **kwargs):
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if len(peripheral["sampler_ports"]) != 2:
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if len(peripheral["sampler_ports"]) != 2:
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raise ValueError("wrong number of Sampler ports")
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raise ValueError("wrong number of Sampler ports")
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urukul_ports = []
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urukul_ports = []
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@ -63,17 +65,17 @@ def peripheral_suservo(module, peripheral):
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urukul_ports.append(peripheral["urukul1_ports"])
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urukul_ports.append(peripheral["urukul1_ports"])
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eem.SUServo.add_std(module,
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eem.SUServo.add_std(module,
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peripheral["sampler_ports"],
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peripheral["sampler_ports"],
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urukul_ports)
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urukul_ports, **kwargs)
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def peripheral_zotino(module, peripheral):
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def peripheral_zotino(module, peripheral, **kwargs):
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if len(peripheral["ports"]) != 1:
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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raise ValueError("wrong number of ports")
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eem.Zotino.add_std(module, peripheral["ports"][0],
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eem.Zotino.add_std(module, peripheral["ports"][0],
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ttl_serdes_7series.Output_8X)
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ttl_serdes_7series.Output_8X, **kwargs)
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def peripheral_grabber(module, peripheral):
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def peripheral_grabber(module, peripheral, **kwargs):
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if len(peripheral["ports"]) == 1:
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if len(peripheral["ports"]) == 1:
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port = peripheral["ports"][0]
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port = peripheral["ports"][0]
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port_aux = None
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port_aux = None
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@ -85,27 +87,27 @@ def peripheral_grabber(module, peripheral):
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port, port_aux, port_aux2 = peripheral["ports"]
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port, port_aux, port_aux2 = peripheral["ports"]
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else:
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else:
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raise ValueError("wrong number of ports")
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raise ValueError("wrong number of ports")
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eem.Grabber.add_std(module, port, port_aux, port_aux2)
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eem.Grabber.add_std(module, port, port_aux, port_aux2, **kwargs)
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def peripheral_mirny(module, peripheral):
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def peripheral_mirny(module, peripheral, **kwargs):
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if len(peripheral["ports"]) != 1:
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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raise ValueError("wrong number of ports")
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eem.Mirny.add_std(module, peripheral["ports"][0],
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eem.Mirny.add_std(module, peripheral["ports"][0],
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ttl_serdes_7series.Output_8X)
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ttl_serdes_7series.Output_8X, **kwargs)
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def peripheral_fastino(module, peripheral):
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def peripheral_fastino(module, peripheral, **kwargs):
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if len(peripheral["ports"]) != 1:
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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raise ValueError("wrong number of ports")
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eem.Fastino.add_std(module, peripheral["ports"][0],
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eem.Fastino.add_std(module, peripheral["ports"][0],
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peripheral["log2_width"])
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peripheral["log2_width"], **kwargs)
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def peripheral_phaser(module, peripheral):
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def peripheral_phaser(module, peripheral, **kwargs):
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if len(peripheral["ports"]) != 1:
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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raise ValueError("wrong number of ports")
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eem.Phaser.add_std(module, peripheral["ports"][0])
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eem.Phaser.add_std(module, peripheral["ports"][0], **kwargs)
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peripheral_processors = {
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peripheral_processors = {
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@ -122,6 +124,6 @@ peripheral_processors = {
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}
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}
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def add_peripherals(module, peripherals):
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def add_peripherals(module, peripherals, **kwargs):
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for peripheral in peripherals:
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for peripheral in peripherals:
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peripheral_processors[peripheral["type"]](module, peripheral)
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peripheral_processors[peripheral["type"]](module, peripheral, **kwargs)
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