diff --git a/artiq/gateware/eem_7series.py b/artiq/gateware/eem_7series.py
index 728db3e2e..bbd883a83 100644
--- a/artiq/gateware/eem_7series.py
+++ b/artiq/gateware/eem_7series.py
@@ -2,7 +2,7 @@ from artiq.gateware import eem
 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, edge_counter
 
 
-def peripheral_dio(module, peripheral):
+def peripheral_dio(module, peripheral, **kwargs):
     ttl_classes = {
         "input": ttl_serdes_7series.InOut_8X,
         "output": ttl_serdes_7series.Output_8X
@@ -16,10 +16,10 @@ def peripheral_dio(module, peripheral):
     eem.DIO.add_std(module, peripheral["ports"][0],
         ttl_classes[peripheral["bank_direction_low"]],
         ttl_classes[peripheral["bank_direction_high"]],
-        edge_counter_cls=edge_counter_cls)
+        edge_counter_cls=edge_counter_cls, **kwargs)
 
 
-def peripheral_urukul(module, peripheral):
+def peripheral_urukul(module, peripheral, **kwargs):
     if len(peripheral["ports"]) == 1:
         port, port_aux = peripheral["ports"][0], None
     elif len(peripheral["ports"]) == 2:
@@ -31,26 +31,28 @@ def peripheral_urukul(module, peripheral):
     else:
         sync_gen_cls = None
     eem.Urukul.add_std(module, port, port_aux, ttl_serdes_7series.Output_8X,
-        sync_gen_cls)
+        sync_gen_cls, **kwargs)
 
 
-def peripheral_novogorny(module, peripheral):
+def peripheral_novogorny(module, peripheral, **kwargs):
     if len(peripheral["ports"]) != 1:
         raise ValueError("wrong number of ports")
-    eem.Novogorny.add_std(module, peripheral["ports"][0], ttl_serdes_7series.Output_8X)
+    eem.Novogorny.add_std(module, peripheral["ports"][0],
+        ttl_serdes_7series.Output_8X, **kwargs)
 
 
-def peripheral_sampler(module, peripheral):
+def peripheral_sampler(module, peripheral, **kwargs):
     if len(peripheral["ports"]) == 1:
         port, port_aux = peripheral["ports"][0], None
     elif len(peripheral["ports"]) == 2:
         port, port_aux = peripheral["ports"]
     else:
         raise ValueError("wrong number of ports")
-    eem.Sampler.add_std(module, port, port_aux, ttl_serdes_7series.Output_8X)
+    eem.Sampler.add_std(module, port, port_aux, ttl_serdes_7series.Output_8X,
+        **kwargs)
 
 
-def peripheral_suservo(module, peripheral):
+def peripheral_suservo(module, peripheral, **kwargs):
     if len(peripheral["sampler_ports"]) != 2:
         raise ValueError("wrong number of Sampler ports")
     urukul_ports = []
@@ -63,17 +65,17 @@ def peripheral_suservo(module, peripheral):
         urukul_ports.append(peripheral["urukul1_ports"])
     eem.SUServo.add_std(module,
         peripheral["sampler_ports"],
-        urukul_ports)
+        urukul_ports, **kwargs)
 
 
-def peripheral_zotino(module, peripheral):
+def peripheral_zotino(module, peripheral, **kwargs):
     if len(peripheral["ports"]) != 1:
         raise ValueError("wrong number of ports")
     eem.Zotino.add_std(module, peripheral["ports"][0],
-        ttl_serdes_7series.Output_8X)
+        ttl_serdes_7series.Output_8X, **kwargs)
 
 
-def peripheral_grabber(module, peripheral):
+def peripheral_grabber(module, peripheral, **kwargs):
     if len(peripheral["ports"]) == 1:
         port = peripheral["ports"][0]
         port_aux = None
@@ -85,27 +87,27 @@ def peripheral_grabber(module, peripheral):
         port, port_aux, port_aux2 = peripheral["ports"]
     else:
         raise ValueError("wrong number of ports")
-    eem.Grabber.add_std(module, port, port_aux, port_aux2)
+    eem.Grabber.add_std(module, port, port_aux, port_aux2, **kwargs)
 
 
-def peripheral_mirny(module, peripheral):
+def peripheral_mirny(module, peripheral, **kwargs):
     if len(peripheral["ports"]) != 1:
         raise ValueError("wrong number of ports")
     eem.Mirny.add_std(module, peripheral["ports"][0],
-        ttl_serdes_7series.Output_8X)
+        ttl_serdes_7series.Output_8X, **kwargs)
 
 
-def peripheral_fastino(module, peripheral):
+def peripheral_fastino(module, peripheral, **kwargs):
     if len(peripheral["ports"]) != 1:
         raise ValueError("wrong number of ports")
     eem.Fastino.add_std(module, peripheral["ports"][0],
-        peripheral["log2_width"])
+        peripheral["log2_width"], **kwargs)
 
 
-def peripheral_phaser(module, peripheral):
+def peripheral_phaser(module, peripheral, **kwargs):
     if len(peripheral["ports"]) != 1:
         raise ValueError("wrong number of ports")
-    eem.Phaser.add_std(module, peripheral["ports"][0])
+    eem.Phaser.add_std(module, peripheral["ports"][0], **kwargs)
 
 
 peripheral_processors = {
@@ -122,6 +124,6 @@ peripheral_processors = {
 }
 
 
-def add_peripherals(module, peripherals):
+def add_peripherals(module, peripherals, **kwargs):
     for peripheral in peripherals:
-        peripheral_processors[peripheral["type"]](module, peripheral)
+        peripheral_processors[peripheral["type"]](module, peripheral, **kwargs)