mirror of https://github.com/m-labs/artiq.git
Merge branch 'master' into new
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commit
53e79f553f
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@ -101,6 +101,8 @@ class AD9910:
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self.pll_vco = pll_vco
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assert 0 <= pll_cp <= 7
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self.pll_cp = pll_cp
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if sync_delay_seed >= 0 and not self.cpld.sync_div:
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raise ValueError("parent cpld does not drive SYNC")
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self.sync_delay_seed = sync_delay_seed
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self.io_update_delay = io_update_delay
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self.phase_mode = PHASE_MODE_CONTINUOUS
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@ -430,6 +432,8 @@ class AD9910:
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Defaults to 15 (half range).
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:return: Tuple of optimal delay and window size.
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"""
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if not self.cpld.sync_div:
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raise ValueError("parent cpld does not drive SYNC")
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search_span = 31
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# FIXME https://github.com/sinara-hw/Urukul/issues/16
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# should both be 2-4 once kasli sync_in jitter is identified
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@ -175,6 +175,10 @@ class AD9914:
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accumulator is set to the value it would have if the DDS had been
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running at the specified frequency since the start of the
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experiment.
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.. warning:: This setting may become inconsistent when used as part of
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a DMA recording. When using DMA, it is recommended to specify the
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phase mode explicitly when calling :meth:`set` or :meth:`set_mu`.
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"""
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self.phase_mode = phase_mode
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@ -190,6 +194,11 @@ class AD9914:
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The "frequency update" pulse is sent to the DDS with a fixed latency
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with respect to the current position of the time cursor.
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When switching from other phase modes to the continuous phase mode,
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there is no jump in the DDS phase. This is however not true when
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using the continuous phase mode after playing back a DMA sequence
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that contained the other phase modes.
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:param ftw: frequency to generate.
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:param pow: adds an offset to the phase.
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:param phase_mode: if specified, overrides the default phase mode set
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@ -186,6 +186,12 @@ class SPIMaster:
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This method is portable and can also be called from e.g.
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:meth:`__init__`.
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.. warning:: If this method is called while recording a DMA
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sequence, the playback of the sequence will not update the
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driver state.
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When required, update the driver state manually (by calling
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this method) after playing back a DMA sequence.
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:param div: SPI clock divider (see: :meth:`set_config_mu`)
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:param length: SPI transfer length (see: :meth:`set_config_mu`)
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"""
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@ -107,12 +107,22 @@ class TTLInOut:
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:param channel: channel number
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"""
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kernel_invariants = {"core", "channel",
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kernel_invariants = {"core", "channel", "gate_latency_mu",
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"target_o", "target_oe", "target_sens", "target_sample"}
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def __init__(self, dmgr, channel, core_device="core"):
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def __init__(self, dmgr, channel, gate_latency_mu=None,
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core_device="core"):
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self.core = dmgr.get(core_device)
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self.channel = channel
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# With TTLs inputs, the gate control is connected to a high-latency
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# path through SED. When looking at the RTIO counter to determine if
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# the gate has closed, we need to take this latency into account.
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# See: https://github.com/m-labs/artiq/issues/1137
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if gate_latency_mu is None:
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gate_latency_mu = 13*self.core.ref_multiplier
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self.gate_latency_mu = gate_latency_mu
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self.target_o = (channel << 8) + 0
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self.target_oe = (channel << 8) + 1
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self.target_sens = (channel << 8) + 2
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@ -329,7 +339,7 @@ class TTLInOut:
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ttl_input.count(ttl_input.gate_rising(100 * us))
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"""
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count = 0
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while rtio_input_timestamp(up_to_timestamp_mu, self.channel) >= 0:
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while rtio_input_timestamp(up_to_timestamp_mu + self.gate_latency_mu, self.channel) >= 0:
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count += 1
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return count
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@ -352,7 +362,7 @@ class TTLInOut:
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:return: The timestamp (in machine units) of the first event received;
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-1 on timeout.
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"""
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return rtio_input_timestamp(up_to_timestamp_mu, self.channel)
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return rtio_input_timestamp(up_to_timestamp_mu + self.gate_latency_mu, self.channel)
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# Input API: sampling
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@kernel
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@ -420,7 +430,7 @@ class TTLInOut:
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rtio_output(self.target_sens, 0)
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success = True
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try:
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while rtio_input_timestamp(now_mu(), self.channel) != -1:
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while rtio_input_timestamp(now_mu() + self.gate_latency_mu, self.channel) != -1:
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success = False
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except RTIOOverflow:
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success = False
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@ -309,15 +309,17 @@ class CPLD:
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def get_att_mu(self):
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"""Return the digital step attenuator settings in machine units.
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This method will also (as a side effect) write the attenuator
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settings of all four channels.
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:return: 32 bit attenuator settings
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"""
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT, 32,
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_INPUT, 32,
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SPIT_ATT_RD, CS_ATT)
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self.bus.write(self.att_reg)
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return self.bus.read()
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self.bus.write(0) # shift in zeros, shift out current value
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self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, 32,
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SPIT_ATT_WR, CS_ATT)
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delay(10*us)
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self.att_reg = self.bus.read()
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self.bus.write(self.att_reg) # shift in current value again and latch
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return self.att_reg
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@kernel
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def set_sync_div(self, div):
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@ -1186,24 +1186,26 @@ class VLBAISatellite(_SatelliteBase):
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self.add_rtio(self.rtio_channels)
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VARIANTS = {cls.__name__.lower(): cls for cls in [
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Opticlock, SUServo, PTB, PTB2, HUB, LUH,
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SYSU, MITLL, MITLL2, USTC, Tsinghua, Tsinghua2, WIPM, NUDT,
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VLBAIMaster, VLBAISatellite, Tester, Master, Satellite]}
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder for Kasli systems")
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builder_args(parser)
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soc_kasli_args(parser)
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parser.set_defaults(output_dir="artiq_kasli")
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variants = {cls.__name__.lower(): cls for cls in [
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Opticlock, SUServo, PTB, PTB2, HUB, LUH,
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SYSU, MITLL, MITLL2, USTC, Tsinghua, Tsinghua2, WIPM, NUDT,
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VLBAIMaster, VLBAISatellite, Tester, Master, Satellite]}
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parser.add_argument("-V", "--variant", default="opticlock",
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help="variant: {} (default: %(default)s)".format(
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"/".join(sorted(variants.keys()))))
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"/".join(sorted(VARIANTS.keys()))))
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args = parser.parse_args()
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variant = args.variant.lower()
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try:
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cls = variants[variant]
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cls = VARIANTS[variant]
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except KeyError:
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raise SystemExit("Invalid variant (-V/--variant)")
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@ -402,6 +402,9 @@ class SMA_SPI(_StandaloneBase):
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self.csr_devices.append("rtio_analyzer")
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VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_QC2, SMA_SPI]}
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def main():
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parser = argparse.ArgumentParser(
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description="KC705 gateware and firmware builder")
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args = parser.parse_args()
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variant = args.variant.lower()
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if variant == "nist_clock":
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cls = NIST_CLOCK
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elif variant == "nist_qc2":
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cls = NIST_QC2
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elif variant == "sma_spi":
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cls = SMA_SPI
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else:
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try:
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cls = VARIANTS[variant]
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except KeyError:
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raise SystemExit("Invalid variant (-V/--variant)")
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soc = cls(**soc_kc705_argdict(args))
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@ -206,6 +206,66 @@ class LoopbackCount(EnvExperiment):
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self.set_dataset("count", self.loop_in.count(now_mu()))
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class IncorrectPulseTiming(Exception):
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pass
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class LoopbackGateTiming(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("loop_in")
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self.setattr_device("loop_out")
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@kernel
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def run(self):
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# Make sure there are no leftover events.
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self.core.reset()
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self.loop_in.input()
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self.loop_out.output()
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delay_mu(500)
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self.loop_out.off()
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delay_mu(5000)
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# Determine loop delay.
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with parallel:
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self.loop_in.gate_rising_mu(10000)
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with sequential:
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delay_mu(5000)
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out_mu = now_mu()
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self.loop_out.pulse_mu(1000)
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in_mu = self.loop_in.timestamp_mu(now_mu())
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if in_mu < 0:
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raise PulseNotReceived("Cannot determine loop delay")
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loop_delay_mu = in_mu - out_mu
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# With the exact delay known, make sure tight gate timings work.
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# In the most common configuration, 24 mu == 24 ns == 3 coarse periods,
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# which should be plenty of slack.
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delay_mu(10000)
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gate_start_mu = now_mu()
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self.loop_in.gate_both_mu(24)
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gate_end_mu = now_mu()
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# gateware latency offset between gate and input
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lat_offset = 12*8
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out_mu = gate_start_mu - loop_delay_mu + lat_offset
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at_mu(out_mu)
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self.loop_out.pulse_mu(24)
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in_mu = self.loop_in.timestamp_mu(gate_end_mu)
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if in_mu < 0:
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raise PulseNotReceived()
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if not (gate_start_mu <= (in_mu - lat_offset) <= gate_end_mu):
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raise IncorrectPulseTiming("Input event should occur during gate")
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if not (-2 < (in_mu - out_mu - loop_delay_mu) < 2):
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raise IncorrectPulseTiming("Loop delay should not change")
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in_mu = self.loop_in.timestamp_mu(gate_end_mu)
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if in_mu > 0:
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raise IncorrectPulseTiming("Only one pulse should be received")
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class IncorrectLevel(Exception):
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pass
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@ -430,6 +490,9 @@ class CoredeviceTest(ExperimentCase):
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count = self.dataset_mgr.get("count")
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self.assertEqual(count, npulses)
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def test_loopback_gate_timing(self):
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self.execute(LoopbackGateTiming)
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def test_level(self):
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self.execute(Level)
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