examples: add Kasli SAWG master

artiq/examples/kasli_sawgmaster/device_db.py

@@ -0,0 +1,42 @@
+core_addr = "kasli-1.lab.m-labs.hk"
+
+device_db = {
+    "core": {
+        "type": "local",
+        "module": "artiq.coredevice.core",
+        "class": "Core",
+        "arguments": {"host": core_addr, "ref_period": 1/(8*150e6)}
+    },
+    "core_log": {
+        "type": "controller",
+        "host": "::1",
+        "port": 1068,
+        "command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
+    },
+    "core_cache": {
+        "type": "local",
+        "module": "artiq.coredevice.cache",
+        "class": "CoreCache"
+    },
+    "core_dma": {
+        "type": "local",
+        "module": "artiq.coredevice.dma",
+        "class": "CoreDMA"
+    },
+}
+
+for i in range(8):
+    device_db["sawg" + str(i)] = {
+        "type": "local",
+        "module": "artiq.coredevice.sawg",
+        "class": "SAWG",
+        "arguments": {"channel_base": i*10+0x010006, "parallelism": 4}
+    }
+
+for i in range(8):
+    device_db["sawg" + str(8+i)] = {
+        "type": "local",
+        "module": "artiq.coredevice.sawg",
+        "class": "SAWG",
+        "arguments": {"channel_base": i*10+0x020006, "parallelism": 4}
+    }

artiq/examples/kasli_sawgmaster/repository/sines_drtio.py

@@ -0,0 +1,27 @@
+from artiq.experiment import *
+
+
+class SAWGTestDRTIO(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.sawgs = [self.get_device("sawg"+str(i)) for i in range(16)]
+
+    @kernel
+    def run(self):
+        while True:
+            print("waiting for DRTIO ready...")
+            while not (self.core.get_drtio_link_status(0) and
+                       self.core.get_drtio_link_status(1)):
+                pass
+            print("OK")
+
+            self.core.reset()
+
+            for sawg in self.sawgs:
+                delay(1*ms)
+                sawg.amplitude1.set(.4)
+                # Do not use a sub-multiple of oscilloscope sample rates.
+                sawg.frequency0.set(9*MHz)
+
+            while self.core.get_drtio_link_status(0) and self.core.get_drtio_link_status(1):
+                pass