M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

rtio: fix timestamp shift

This commit is contained in:
Sebastien Bourdeauducq 2016-11-23 13:36:30 +08:00
parent 5a2edef422
commit 4e931c7dd2
1 changed files with 5 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
artiq/gateware/rtio/core.py
View File

@ -265,7 +265,7 @@ class LogChannel:
class Core(Module): class Core(Module):
def __init__(self, channels, full_ts_width=63, guard_io_cycles=20): def __init__(self, channels, guard_io_cycles=20):
data_width = max(rtlink.get_data_width(c.interface) data_width = max(rtlink.get_data_width(c.interface)
for c in channels) for c in channels)
address_width = max(rtlink.get_address_width(c.interface) address_width = max(rtlink.get_address_width(c.interface)
@ -309,7 +309,7 @@ class Core(Module):
cmd_reset_phy | ResetSignal("rtio", allow_reset_less=True)) cmd_reset_phy | ResetSignal("rtio", allow_reset_less=True))
# Managers # Managers
self.submodules.counter = RTIOCounter(full_ts_width - fine_ts_width) self.submodules.counter = RTIOCounter(len(self.cri.o_timestamp) - fine_ts_width)
i_datas, i_timestamps = [], [] i_datas, i_timestamps = [], []
o_statuses, i_statuses = [], [] o_statuses, i_statuses = [], []
@ -333,10 +333,10 @@ class Core(Module):
if hasattr(o_manager.ev, "address"): if hasattr(o_manager.ev, "address"):
self.comb += o_manager.ev.address.eq(self.cri.o_address) self.comb += o_manager.ev.address.eq(self.cri.o_address)
ts_shift = len(self.cri.o_timestamp) - len(o_manager.ev.timestamp) ts_shift = len(self.cri.o_timestamp) - len(o_manager.ev.timestamp)
print(n, ts_shift, channel)
self.comb += o_manager.ev.timestamp.eq(self.cri.o_timestamp[ts_shift:]) self.comb += o_manager.ev.timestamp.eq(self.cri.o_timestamp[ts_shift:])
self.comb += o_manager.we.eq(selected & self.comb += o_manager.we.eq(selected & (self.cri.cmd == cri.commands["write"]))
(self.cri.cmd == cri.commands["write"]))
underflow = Signal() underflow = Signal()
sequence_error = Signal() sequence_error = Signal()
@ -372,8 +372,7 @@ class Core(Module):
else: else:
i_datas.append(0) i_datas.append(0)
if channel.interface.i.timestamped: if channel.interface.i.timestamped:
ts_shift = (len(self.cri.i_timestamp) ts_shift = (len(self.cri.i_timestamp) - len(i_manager.ev.timestamp))
- len(i_manager.ev.timestamp))
i_timestamps.append(i_manager.ev.timestamp << ts_shift) i_timestamps.append(i_manager.ev.timestamp << ts_shift)
else: else:
i_timestamps.append(0) i_timestamps.append(0)