From 4e931c7dd2ab3831dffd9583a27f5129a7031bca Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 23 Nov 2016 13:36:30 +0800 Subject: [PATCH] rtio: fix timestamp shift --- artiq/gateware/rtio/core.py | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/artiq/gateware/rtio/core.py b/artiq/gateware/rtio/core.py index 4c8e16929..da7e2e02b 100644 --- a/artiq/gateware/rtio/core.py +++ b/artiq/gateware/rtio/core.py @@ -265,7 +265,7 @@ class LogChannel: class Core(Module): - def __init__(self, channels, full_ts_width=63, guard_io_cycles=20): + def __init__(self, channels, guard_io_cycles=20): data_width = max(rtlink.get_data_width(c.interface) for c in channels) address_width = max(rtlink.get_address_width(c.interface) @@ -309,7 +309,7 @@ class Core(Module): cmd_reset_phy | ResetSignal("rtio", allow_reset_less=True)) # Managers - self.submodules.counter = RTIOCounter(full_ts_width - fine_ts_width) + self.submodules.counter = RTIOCounter(len(self.cri.o_timestamp) - fine_ts_width) i_datas, i_timestamps = [], [] o_statuses, i_statuses = [], [] @@ -333,10 +333,10 @@ class Core(Module): if hasattr(o_manager.ev, "address"): self.comb += o_manager.ev.address.eq(self.cri.o_address) ts_shift = len(self.cri.o_timestamp) - len(o_manager.ev.timestamp) + print(n, ts_shift, channel) self.comb += o_manager.ev.timestamp.eq(self.cri.o_timestamp[ts_shift:]) - self.comb += o_manager.we.eq(selected & - (self.cri.cmd == cri.commands["write"])) + self.comb += o_manager.we.eq(selected & (self.cri.cmd == cri.commands["write"])) underflow = Signal() sequence_error = Signal() @@ -372,8 +372,7 @@ class Core(Module): else: i_datas.append(0) if channel.interface.i.timestamped: - ts_shift = (len(self.cri.i_timestamp) - - len(i_manager.ev.timestamp)) + ts_shift = (len(self.cri.i_timestamp) - len(i_manager.ev.timestamp)) i_timestamps.append(i_manager.ev.timestamp << ts_shift) else: i_timestamps.append(0)