mirror of https://github.com/m-labs/artiq.git
firmware: run PRBS and STPL JESD204 tests
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03007b896e
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4b3baf4825
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@ -350,7 +350,6 @@ pub fn setup(dacno: u8, linerate: u64) -> Result<(), &'static str> {
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0x1*ad9154_reg::LINK_EN | 0*ad9154_reg::LINK_PAGE |
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0*ad9154_reg::LINK_MODE | 0*ad9154_reg::CHECKSUM_MODE);
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info!(" ...done");
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status(dacno);
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Ok(())
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}
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@ -1,37 +0,0 @@
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use board_misoc::csr;
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pub fn jesd_reset(reset: bool) {
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unsafe {
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csr::jesd_crg::jreset_write(if reset {1} else {0});
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}
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}
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pub fn jesd_enable(dacno: u8, en: bool) {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_enable_write)(if en {1} else {0})
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}
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}
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pub fn jesd_ready(dacno: u8) -> bool {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_ready_read)() != 0
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}
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}
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pub fn jesd_prbs(dacno: u8, en: bool) {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_prbs_config_write)(if en {0b01} else {0b00})
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}
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}
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pub fn jesd_stpl(dacno: u8, en: bool) {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_stpl_enable_write)(if en {1} else {0})
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}
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}
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pub fn jesd_jsync(dacno: u8) -> bool {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_jsync_read)() != 0
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}
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}
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@ -42,8 +42,6 @@ mod ad9154_reg;
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pub mod ad9154;
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/* TODO: #[cfg(has_jdcg)]
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pub mod jesd204sync; */
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#[cfg(has_jdcg)]
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pub mod jdcg;
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#[cfg(has_allaki_atts)]
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pub mod hmc542;
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@ -54,7 +54,7 @@ pub enum Packet {
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SpiReadReply { succeeded: bool, data: u32 },
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SpiBasicReply { succeeded: bool },
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JdacSetupRequest { destination: u8, dacno: u8 },
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JdacBasicRequest { destination: u8, dacno: u8, reqno: u8 },
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JdacBasicReply { succeeded: bool },
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}
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@ -181,9 +181,10 @@ impl Packet {
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succeeded: reader.read_bool()?
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},
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0xa0 => Packet::JdacSetupRequest {
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0xa0 => Packet::JdacBasicRequest {
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destination: reader.read_u8()?,
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dacno: reader.read_u8()?,
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reqno: reader.read_u8()?,
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},
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0xa1 => Packet::JdacBasicReply {
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succeeded: reader.read_bool()?
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@ -341,10 +342,11 @@ impl Packet {
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writer.write_bool(succeeded)?;
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},
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Packet::JdacSetupRequest { destination, dacno } => {
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Packet::JdacBasicRequest { destination, dacno, reqno } => {
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writer.write_u8(0xa0)?;
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writer.write_u8(destination)?;
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writer.write_u8(dacno)?;
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writer.write_u8(reqno)?;
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}
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Packet::JdacBasicReply { succeeded } => {
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writer.write_u8(0xa1)?;
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@ -0,0 +1,98 @@
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use board_misoc::{csr, clock};
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use board_artiq::drtioaux;
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pub fn jesd_reset(reset: bool) {
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unsafe {
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csr::jesd_crg::jreset_write(if reset {1} else {0});
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}
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}
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fn jesd_enable(dacno: u8, en: bool) {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_enable_write)(if en {1} else {0})
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}
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clock::spin_us(5000);
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}
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fn jesd_ready(dacno: u8) -> bool {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_ready_read)() != 0
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}
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}
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fn jesd_prbs(dacno: u8, en: bool) {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_prbs_config_write)(if en {0b01} else {0b00})
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}
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clock::spin_us(5000);
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}
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fn jesd_stpl(dacno: u8, en: bool) {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_stpl_enable_write)(if en {1} else {0})
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}
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clock::spin_us(5000);
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}
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fn jesd_jsync(dacno: u8) -> bool {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_jsync_read)() != 0
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}
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}
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fn jdac_basic_request(dacno: u8, reqno: u8) {
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if let Err(e) = drtioaux::send(1, &drtioaux::Packet::JdacBasicRequest {
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destination: 0,
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dacno: dacno,
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reqno: reqno
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}) {
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error!("aux packet error ({})", e);
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}
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match drtioaux::recv_timeout(1, Some(1000)) {
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Ok(drtioaux::Packet::JdacBasicReply { succeeded }) =>
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if !succeeded {
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error!("JESD DAC basic request failed (dacno={}, reqno={})", dacno, reqno);
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},
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Ok(packet) => error!("received unexpected aux packet: {:?}", packet),
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Err(e) => error!("aux packet error ({})", e),
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}
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}
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pub fn init() {
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for dacno in 0..csr::JDCG.len() {
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let dacno = dacno as u8;
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info!("DAC-{} initializing...", dacno);
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jesd_enable(dacno, true);
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jesd_prbs(dacno, false);
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jesd_stpl(dacno, false);
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jdac_basic_request(dacno, 0);
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jesd_prbs(dacno, true);
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jdac_basic_request(dacno, 2);
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jesd_prbs(dacno, false);
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jesd_stpl(dacno, true);
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jdac_basic_request(dacno, 3);
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jesd_stpl(dacno, false);
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jdac_basic_request(dacno, 0);
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let t = clock::get_ms();
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while !jesd_ready(dacno) {
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if clock::get_ms() > t + 200 {
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error!("JESD ready timeout");
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break;
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}
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}
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clock::spin_us(5000);
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jdac_basic_request(dacno, 1);
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if !jesd_jsync(dacno) {
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error!("bad SYNC");
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}
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info!(" ...done");
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}
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}
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@ -15,6 +15,8 @@ use board_artiq::drtio_routing;
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use board_artiq::hmc830_7043;
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mod repeater;
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#[cfg(has_jdcg)]
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mod jdcg;
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fn drtiosat_reset(reset: bool) {
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unsafe {
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@ -288,7 +290,7 @@ fn process_aux_packet(_repeaters: &mut [repeater::Repeater],
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}
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}
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drtioaux::Packet::JdacSetupRequest { destination: _destination, dacno: _dacno } => {
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drtioaux::Packet::JdacBasicRequest { destination: _destination, dacno: _dacno, reqno: _reqno } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet);
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#[cfg(has_ad9154)]
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let succeeded = {
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@ -296,7 +298,13 @@ fn process_aux_packet(_repeaters: &mut [repeater::Repeater],
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const LINERATE: u64 = 5_000_000_000;
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#[cfg(rtio_frequency = "150.0")]
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const LINERATE: u64 = 6_000_000_000;
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board_artiq::ad9154::setup(_dacno, LINERATE).is_ok()
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match _reqno {
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0 => board_artiq::ad9154::setup(_dacno, LINERATE).is_ok(),
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1 => { board_artiq::ad9154::status(_dacno); true },
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2 => board_artiq::ad9154::prbs(_dacno).is_ok(),
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3 => board_artiq::ad9154::stpl(_dacno, 4, 2).is_ok(),
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_ => false
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}
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};
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#[cfg(not(has_ad9154))]
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let succeeded = false;
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@ -416,41 +424,6 @@ const SI5324_SETTINGS: si5324::FrequencySettings
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crystal_ref: true
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};
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#[cfg(has_jdcg)]
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fn init_jdcgs() {
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for dacno in 0..csr::JDCG.len() {
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let dacno = dacno as u8;
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info!("DAC-{} initializing...", dacno);
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board_artiq::jdcg::jesd_enable(dacno, false);
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board_artiq::jdcg::jesd_prbs(dacno, false);
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board_artiq::jdcg::jesd_stpl(dacno, false);
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clock::spin_us(10000);
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board_artiq::jdcg::jesd_enable(dacno, true);
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let t = clock::get_ms();
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while !board_artiq::jdcg::jesd_ready(dacno) {
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if clock::get_ms() > t + 200 {
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error!("JESD ready timeout");
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break;
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}
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}
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if let Err(e) = drtioaux::send(1, &drtioaux::Packet::JdacSetupRequest {
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destination: 0,
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dacno: dacno
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}) {
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error!("aux packet error ({})", e);
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}
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match drtioaux::recv_timeout(1, Some(1000)) {
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Ok(drtioaux::Packet::JdacBasicReply { succeeded }) =>
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if !succeeded { error!("DAC-{} initialization failed", dacno); },
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Ok(packet) => error!("received unexpected aux packet: {:?}", packet),
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Err(e) => error!("aux packet error ({})", e),
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}
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info!(" ...done");
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}
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}
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#[no_mangle]
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pub extern fn main() -> i32 {
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clock::init();
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@ -523,9 +496,9 @@ pub extern fn main() -> i32 {
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* To handle those cases, we simply keep the JESD204 core in reset unless the
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* Si5324 is locked to the recovered clock.
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*/
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board_artiq::jdcg::jesd_reset(false);
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jdcg::jesd_reset(false);
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if repeaters[0].is_up() {
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init_jdcgs();
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jdcg::init();
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}
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}
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@ -545,7 +518,7 @@ pub extern fn main() -> i32 {
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{
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let rep0_is_up = repeaters[0].is_up();
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if rep0_is_up && !rep0_was_up {
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init_jdcgs();
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jdcg::init();
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}
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rep0_was_up = rep0_is_up;
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}
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@ -573,7 +546,7 @@ pub extern fn main() -> i32 {
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}
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#[cfg(has_jdcg)]
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board_artiq::jdcg::jesd_reset(true);
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jdcg::jesd_reset(true);
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drtiosat_reset_phy(true);
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drtiosat_reset(true);
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