firmware: run PRBS and STPL JESD204 tests

artiq/firmware/libboard_artiq/ad9154.rs

@@ -350,7 +350,6 @@ pub fn setup(dacno: u8, linerate: u64) -> Result<(), &'static str> {
             0x1*ad9154_reg::LINK_EN | 0*ad9154_reg::LINK_PAGE |
             0*ad9154_reg::LINK_MODE | 0*ad9154_reg::CHECKSUM_MODE);
     info!("  ...done");
-    status(dacno);
     Ok(())
 }
 

artiq/firmware/libboard_artiq/jdcg.rs

@@ -1,37 +0,0 @@
-use board_misoc::csr;
-
-pub fn jesd_reset(reset: bool) {
-    unsafe {
-        csr::jesd_crg::jreset_write(if reset {1} else {0});
-    }
-}
-
-pub fn jesd_enable(dacno: u8, en: bool) {
-    unsafe {
-        (csr::JDCG[dacno as usize].jesd_control_enable_write)(if en {1} else {0})
-    }
-}
-
-pub fn jesd_ready(dacno: u8) -> bool {
-    unsafe {
-        (csr::JDCG[dacno as usize].jesd_control_ready_read)() != 0
-    }
-}
-
-pub fn jesd_prbs(dacno: u8, en: bool) {
-    unsafe {
-        (csr::JDCG[dacno as usize].jesd_control_prbs_config_write)(if en {0b01} else {0b00})
-    }
-}
-
-pub fn jesd_stpl(dacno: u8, en: bool) {
-    unsafe {
-        (csr::JDCG[dacno as usize].jesd_control_stpl_enable_write)(if en {1} else {0})
-    }
-}
-
-pub fn jesd_jsync(dacno: u8) -> bool {
-    unsafe {
-        (csr::JDCG[dacno as usize].jesd_control_jsync_read)() != 0
-    }
-}

artiq/firmware/libboard_artiq/lib.rs

@@ -42,8 +42,6 @@ mod ad9154_reg;
 pub mod ad9154;
 /* TODO: #[cfg(has_jdcg)]
 pub mod jesd204sync; */
-#[cfg(has_jdcg)]
-pub mod jdcg;
 #[cfg(has_allaki_atts)]
 pub mod hmc542;
 

artiq/firmware/libproto_artiq/drtioaux_proto.rs

@@ -54,7 +54,7 @@ pub enum Packet {
     SpiReadReply { succeeded: bool, data: u32 },
     SpiBasicReply { succeeded: bool },
 
-    JdacSetupRequest { destination: u8, dacno: u8 },
+    JdacBasicRequest { destination: u8, dacno: u8, reqno: u8 },
     JdacBasicReply { succeeded: bool },
 }
 
@@ -181,9 +181,10 @@ impl Packet {
                 succeeded: reader.read_bool()?
             },
 
-            0xa0 => Packet::JdacSetupRequest {
+            0xa0 => Packet::JdacBasicRequest {
                 destination: reader.read_u8()?,
                 dacno: reader.read_u8()?,
+                reqno: reader.read_u8()?,
             },
             0xa1 => Packet::JdacBasicReply {
                 succeeded: reader.read_bool()?
@@ -341,10 +342,11 @@ impl Packet {
                 writer.write_bool(succeeded)?;
             },
 
-            Packet::JdacSetupRequest { destination, dacno } => {
+            Packet::JdacBasicRequest { destination, dacno, reqno } => {
                 writer.write_u8(0xa0)?;
                 writer.write_u8(destination)?;
                 writer.write_u8(dacno)?;
+                writer.write_u8(reqno)?;
             }
             Packet::JdacBasicReply { succeeded } => {
                 writer.write_u8(0xa1)?;

artiq/firmware/satman/jdcg.rs

@@ -0,0 +1,98 @@
+use board_misoc::{csr, clock};
+use board_artiq::drtioaux;
+
+pub fn jesd_reset(reset: bool) {
+    unsafe {
+        csr::jesd_crg::jreset_write(if reset {1} else {0});
+    }
+}
+
+fn jesd_enable(dacno: u8, en: bool) {
+    unsafe {
+        (csr::JDCG[dacno as usize].jesd_control_enable_write)(if en {1} else {0})
+    }
+    clock::spin_us(5000);
+}
+
+fn jesd_ready(dacno: u8) -> bool {
+    unsafe {
+        (csr::JDCG[dacno as usize].jesd_control_ready_read)() != 0
+    }
+}
+
+fn jesd_prbs(dacno: u8, en: bool) {
+    unsafe {
+        (csr::JDCG[dacno as usize].jesd_control_prbs_config_write)(if en {0b01} else {0b00})
+    }
+    clock::spin_us(5000);
+}
+
+fn jesd_stpl(dacno: u8, en: bool) {
+    unsafe {
+        (csr::JDCG[dacno as usize].jesd_control_stpl_enable_write)(if en {1} else {0})
+    }
+    clock::spin_us(5000);
+}
+
+fn jesd_jsync(dacno: u8) -> bool {
+    unsafe {
+        (csr::JDCG[dacno as usize].jesd_control_jsync_read)() != 0
+    }
+}
+
+fn jdac_basic_request(dacno: u8, reqno: u8) {
+    if let Err(e) = drtioaux::send(1, &drtioaux::Packet::JdacBasicRequest {
+        destination: 0,
+        dacno: dacno,
+        reqno: reqno
+    }) {
+        error!("aux packet error ({})", e);
+    }
+    match drtioaux::recv_timeout(1, Some(1000)) {
+        Ok(drtioaux::Packet::JdacBasicReply { succeeded }) =>
+            if !succeeded {
+                error!("JESD DAC basic request failed (dacno={}, reqno={})", dacno, reqno);
+            },
+        Ok(packet) => error!("received unexpected aux packet: {:?}", packet),
+        Err(e) => error!("aux packet error ({})", e),
+    }
+}
+
+pub fn init() {
+    for dacno in 0..csr::JDCG.len() {
+        let dacno = dacno as u8;
+        info!("DAC-{} initializing...", dacno);
+
+        jesd_enable(dacno, true);
+        jesd_prbs(dacno, false);
+        jesd_stpl(dacno, false);
+
+        jdac_basic_request(dacno, 0);
+
+        jesd_prbs(dacno, true);
+        jdac_basic_request(dacno, 2);
+        jesd_prbs(dacno, false);
+
+        jesd_stpl(dacno, true);
+        jdac_basic_request(dacno, 3);
+        jesd_stpl(dacno, false);
+
+        jdac_basic_request(dacno, 0);
+
+        let t = clock::get_ms();
+        while !jesd_ready(dacno) {
+            if clock::get_ms() > t + 200 {
+                error!("JESD ready timeout");
+                break;
+            }
+        }
+        clock::spin_us(5000);
+        jdac_basic_request(dacno, 1);
+
+        if !jesd_jsync(dacno) {
+            error!("bad SYNC");
+        }
+
+        info!("  ...done");
+    }
+}

artiq/firmware/satman/main.rs

@@ -15,6 +15,8 @@ use board_artiq::drtio_routing;
 use board_artiq::hmc830_7043;
 
 mod repeater;
+#[cfg(has_jdcg)]
+mod jdcg;
 
 fn drtiosat_reset(reset: bool) {
     unsafe {
@@ -288,7 +290,7 @@ fn process_aux_packet(_repeaters: &mut [repeater::Repeater],
             }
         }
 
-        drtioaux::Packet::JdacSetupRequest { destination: _destination, dacno: _dacno } => {
+        drtioaux::Packet::JdacBasicRequest { destination: _destination, dacno: _dacno, reqno: _reqno } => {
             forward!(_routing_table, _destination, *_rank, _repeaters, &packet);
             #[cfg(has_ad9154)]
             let succeeded = {
@@ -296,7 +298,13 @@ fn process_aux_packet(_repeaters: &mut [repeater::Repeater],
                 const LINERATE: u64 = 5_000_000_000;
                 #[cfg(rtio_frequency = "150.0")]
                 const LINERATE: u64 = 6_000_000_000;
-                board_artiq::ad9154::setup(_dacno, LINERATE).is_ok()
+                match _reqno {
+                    0 => board_artiq::ad9154::setup(_dacno, LINERATE).is_ok(),
+                    1 => { board_artiq::ad9154::status(_dacno); true },
+                    2 => board_artiq::ad9154::prbs(_dacno).is_ok(),
+                    3 => board_artiq::ad9154::stpl(_dacno, 4, 2).is_ok(),
+                    _ => false
+                }
             };
             #[cfg(not(has_ad9154))]
             let succeeded = false;
@@ -416,41 +424,6 @@ const SI5324_SETTINGS: si5324::FrequencySettings
     crystal_ref: true
 };
 
-#[cfg(has_jdcg)]
-fn init_jdcgs() {
-    for dacno in 0..csr::JDCG.len() {
-        let dacno = dacno as u8;
-        info!("DAC-{} initializing...", dacno);
-
-        board_artiq::jdcg::jesd_enable(dacno, false);
-        board_artiq::jdcg::jesd_prbs(dacno, false);
-        board_artiq::jdcg::jesd_stpl(dacno, false);
-        clock::spin_us(10000);
-        board_artiq::jdcg::jesd_enable(dacno, true);
-        let t = clock::get_ms();
-        while !board_artiq::jdcg::jesd_ready(dacno) {
-            if clock::get_ms() > t + 200 {
-                error!("JESD ready timeout");
-                break;
-            }
-        }
-
-        if let Err(e) = drtioaux::send(1, &drtioaux::Packet::JdacSetupRequest {
-            destination: 0,
-            dacno: dacno
-        }) {
-            error!("aux packet error ({})", e);
-        }
-        match drtioaux::recv_timeout(1, Some(1000)) {
-            Ok(drtioaux::Packet::JdacBasicReply { succeeded }) =>
-                if !succeeded { error!("DAC-{} initialization failed", dacno); },
-            Ok(packet) => error!("received unexpected aux packet: {:?}", packet),
-            Err(e) => error!("aux packet error ({})", e),
-        }
-        info!("  ...done");
-    }
-}
-
 #[no_mangle]
 pub extern fn main() -> i32 {
     clock::init();
@@ -523,9 +496,9 @@ pub extern fn main() -> i32 {
              * To handle those cases, we simply keep the JESD204 core in reset unless the
              * Si5324 is locked to the recovered clock.
              */
-            board_artiq::jdcg::jesd_reset(false);
+            jdcg::jesd_reset(false);
             if repeaters[0].is_up() {
-                init_jdcgs();
+                jdcg::init();
             }
         }
 
@@ -545,7 +518,7 @@ pub extern fn main() -> i32 {
             {
                 let rep0_is_up = repeaters[0].is_up();
                 if rep0_is_up && !rep0_was_up {
-                    init_jdcgs();
+                    jdcg::init();
                 }
                 rep0_was_up = rep0_is_up;
             }
@@ -573,7 +546,7 @@ pub extern fn main() -> i32 {
         }
 
         #[cfg(has_jdcg)]
-        board_artiq::jdcg::jesd_reset(true);
+        jdcg::jesd_reset(true);
 
         drtiosat_reset_phy(true);
         drtiosat_reset(true);