mirror of https://github.com/m-labs/artiq.git
sayma: 2.4GHz DAC clocking (4X interpolation)
* gets another clock divider out of the way * gets one cycle within range of the HMC7043 analog delay alone * SYSREF/RTIO alignment removed, to be replaced with DDMTD-based scheme
This commit is contained in:
parent
cc9420d2c8
commit
4941fb3300
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@ -184,7 +184,7 @@ fn dac_setup(dacno: u8, linerate: u64) -> Result<(), &'static str> {
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write(ad9154_reg::SPI_PAGEINDX, 0x3); // A and B dual
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write(ad9154_reg::INTERP_MODE, 0x01); // 2x
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write(ad9154_reg::INTERP_MODE, 0x03); // 4x
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write(ad9154_reg::MIX_MODE, 0);
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write(ad9154_reg::DATA_FORMAT, 0*ad9154_reg::BINARY_FORMAT); // s16
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write(ad9154_reg::DATAPATH_CTRL,
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@ -117,6 +117,9 @@ mod hmc830 {
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// Max reference frequency: 350MHz, however f_ref >= 200MHz requires
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// setting 0x08[21]=1
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//
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// Warning: Output divider is not synchronized! Set to 1 for deterministic
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// phase at the output.
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//
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// :param r_div: reference divider [1, 16383]
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// :param n_div: VCO divider, integer part. Integer-N mode: [16, 2**19-1]
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// fractional mode: [20, 2**19-4]
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@ -155,10 +158,11 @@ mod hmc830 {
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pub mod hmc7043 {
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use board_misoc::{csr, clock};
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// All frequencies assume 1.2GHz HMC830 output
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pub const DAC_CLK_DIV: u16 = 1; // 1200MHz
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pub const FPGA_CLK_DIV: u16 = 8; // 150MHz
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pub const SYSREF_DIV: u16 = 128; // 9.375MHz
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// Warning: dividers are not synchronized with HMC830 clock input!
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// Set DAC_CLK_DIV to 1 for deterministic phase.
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pub const DAC_CLK_DIV: u16 = 1; // 2400MHz
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pub const FPGA_CLK_DIV: u16 = 16; // 150MHz
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pub const SYSREF_DIV: u16 = 256; // 9.375MHz
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const HMC_SYSREF_DIV: u16 = SYSREF_DIV*8; // 1.171875MHz (must be <= 4MHz)
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// enabled, divider, output config
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@ -385,35 +389,18 @@ pub mod hmc7043 {
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}
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}
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pub fn sysref_offset_dac(dacno: u8, phase_offset: u16) {
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/* Analog delay resolution: 25ps
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* Digital delay resolution: 1/2 input clock cycle = 416ps for 1.2GHz
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* 16*25ps = 400ps: limit analog delay to 16 steps instead of 32.
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*/
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let analog_delay = (phase_offset % 17) as u8;
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let digital_delay = (phase_offset / 17) as u8;
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pub fn sysref_offset_dac(dacno: u8, phase_offset: u8) {
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spi_setup();
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if dacno == 0 {
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write(0x00d5, analog_delay);
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write(0x00d6, digital_delay);
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write(0x00d5, phase_offset);
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} else if dacno == 1 {
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write(0x00e9, analog_delay);
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write(0x00ea, digital_delay);
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write(0x00e9, phase_offset);
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} else {
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unimplemented!();
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}
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clock::spin_us(100);
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}
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pub fn sysref_offset_fpga(phase_offset: u16) {
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let analog_delay = (phase_offset % 17) as u8;
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let digital_delay = (phase_offset / 17) as u8;
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spi_setup();
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write(0x0111, analog_delay);
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write(0x0112, digital_delay);
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clock::spin_us(100);
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}
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pub fn sysref_slip() {
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spi_setup();
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write(0x0002, 0x02);
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@ -429,11 +416,11 @@ pub fn init() -> Result<(), &'static str> {
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hmc830::detect()?;
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hmc830::init();
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// 1.2GHz out
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// 2.4GHz out
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#[cfg(hmc830_ref = "100")]
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hmc830::set_dividers(1, 24, 0, 2);
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hmc830::set_dividers(1, 24, 0, 1);
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#[cfg(hmc830_ref = "150")]
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hmc830::set_dividers(2, 32, 0, 2);
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hmc830::set_dividers(2, 32, 0, 1);
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hmc830::check_locked()?;
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@ -3,167 +3,7 @@ use board_misoc::{csr, config};
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use hmc830_7043::hmc7043;
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use ad9154;
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fn sysref_sample() -> bool {
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unsafe { csr::sysref_sampler::sample_result_read() == 1 }
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}
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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enum SysrefSample {
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Low,
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High,
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Unstable
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}
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fn sysref_sample_stable(phase_offset: u16) -> SysrefSample {
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hmc7043::sysref_offset_fpga(phase_offset);
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let s1 = sysref_sample();
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hmc7043::sysref_offset_fpga(phase_offset-5);
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let s2 = sysref_sample();
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if s1 == s2 {
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if s1 {
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return SysrefSample::High;
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} else {
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return SysrefSample::Low;
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}
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} else {
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return SysrefSample::Unstable;
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}
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}
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fn sysref_cal_fpga() -> Result<u16, &'static str> {
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info!("calibrating SYSREF phase offset at FPGA...");
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let initial_phase_offset = 136;
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let mut slips0 = 0;
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let mut slips1 = 0;
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// make sure we start in the 0 zone
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while sysref_sample_stable(initial_phase_offset) != SysrefSample::Low {
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hmc7043::sysref_slip();
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slips0 += 1;
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if slips0 > 1024 {
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return Err("failed to reach 1->0 transition (cal)");
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}
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}
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// get near the edge of the 0->1 transition
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while sysref_sample_stable(initial_phase_offset) != SysrefSample::High {
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hmc7043::sysref_slip();
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slips1 += 1;
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if slips1 > 1024 {
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return Err("failed to reach 0->1 transition (cal)");
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}
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}
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for d in 0..initial_phase_offset {
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let phase_offset = initial_phase_offset - d;
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hmc7043::sysref_offset_fpga(phase_offset);
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if !sysref_sample() {
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let result = phase_offset + 17;
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info!(" ...done, phase offset: {}", result);
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return Ok(result);
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}
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}
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return Err("failed to reach 1->0 transition with fine delay");
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}
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fn sysref_rtio_slip_to(target: bool) -> Result<u16, &'static str> {
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let mut slips = 0;
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while sysref_sample() != target {
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hmc7043::sysref_slip();
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slips += 1;
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if slips > 1024 {
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return Err("failed to reach SYSREF transition");
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}
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}
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Ok(slips)
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}
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fn sysref_rtio_check_period(phase_offset: u16) -> Result<(), &'static str> {
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const N: usize = 32;
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let mut nslips = [0; N];
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let mut error = false;
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// meet setup/hold (assuming FPGA timing margins are OK)
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hmc7043::sysref_offset_fpga(phase_offset);
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// if we are already in the 1 zone, get out of it
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sysref_rtio_slip_to(false)?;
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for i in 0..N {
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nslips[i] = sysref_rtio_slip_to(i % 2 == 0)?;
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if nslips[i] != hmc7043::SYSREF_DIV/2 {
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error = true;
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}
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}
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if error {
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info!(" SYSREF slip half-periods: {:?}", nslips);
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return Err("unexpected SYSREF slip half-periods seen");
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} else {
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info!(" SYSREF slip half-periods at FPGA have expected length ({})", hmc7043::SYSREF_DIV/2);
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}
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Ok(())
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}
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fn sysref_rtio_align(phase_offset: u16) -> Result<(), &'static str> {
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// This needs to take place before DAC SYSREF scan, as
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// the HMC7043 input clock (which defines slip resolution)
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// is 2x the DAC clock, so there are two possible phases from
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// the divider states. This deterministically selects one.
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info!("aligning SYSREF with RTIO...");
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sysref_rtio_check_period(phase_offset)?;
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// meet setup/hold (assuming FPGA timing margins are OK)
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hmc7043::sysref_offset_fpga(phase_offset);
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// if we are already in the 1 zone, get out of it
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let slips0 = sysref_rtio_slip_to(false)?;
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// get to the edge of the 0->1 transition (our final setpoint)
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let slips1 = sysref_rtio_slip_to(true)?;
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info!(" ...done ({}/{} slips)", slips0, slips1);
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let mut margin_minus = None;
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for d in 0..phase_offset {
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hmc7043::sysref_offset_fpga(phase_offset - d);
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if !sysref_sample() {
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margin_minus = Some(d);
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break;
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}
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}
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// meet setup/hold
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hmc7043::sysref_offset_fpga(phase_offset);
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if margin_minus.is_some() {
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let margin_minus = margin_minus.unwrap();
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// one phase slip (period of the 1.2GHz input clock)
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let period = 2*17; // approximate: 2 digital coarse delay steps
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let margin_plus = if period > margin_minus { period - margin_minus } else { 0 };
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info!(" margins at FPGA: -{} +{}", margin_minus, margin_plus);
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if margin_minus < 10 || margin_plus < 10 {
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return Err("SYSREF margin at FPGA is too small, board needs recalibration");
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}
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} else {
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return Err("unable to determine SYSREF margin at FPGA");
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}
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Ok(())
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}
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pub fn sysref_auto_rtio_align() -> Result<(), &'static str> {
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let entry = config::read_str("sysref_phase_fpga", |r| r.map(|s| s.parse()));
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let phase_offset = match entry {
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Ok(Ok(phase)) => phase,
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_ => {
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let phase = sysref_cal_fpga()?;
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if let Err(e) = config::write_int("sysref_phase_fpga", phase as u32) {
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error!("failed to update FPGA SYSREF phase in config: {}", e);
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}
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phase
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}
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};
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sysref_rtio_align(phase_offset)
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}
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fn sysref_cal_dac(dacno: u8) -> Result<u16, &'static str> {
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fn sysref_cal_dac(dacno: u8) -> Result<u8, &'static str> {
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info!("calibrating SYSREF phase at DAC-{}...", dacno);
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let mut d = 0;
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@ -182,12 +22,12 @@ fn sysref_cal_dac(dacno: u8) -> Result<u16, &'static str> {
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}
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d += 1;
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if d > 128 {
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if d > 23 {
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return Err("no sync errors found when scanning delay");
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}
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}
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d += 17; // get away from jitter
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d += 5; // get away from jitter
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hmc7043::sysref_offset_dac(dacno, d);
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ad9154::dac_sync(dacno)?;
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@ -200,7 +40,7 @@ fn sysref_cal_dac(dacno: u8) -> Result<u16, &'static str> {
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}
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d += 1;
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if d > 128 {
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if d > 23 {
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return Err("no sync errors found when scanning delay");
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}
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}
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@ -210,7 +50,7 @@ fn sysref_cal_dac(dacno: u8) -> Result<u16, &'static str> {
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Ok(phase)
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}
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fn sysref_dac_align(dacno: u8, phase: u16) -> Result<(), &'static str> {
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fn sysref_dac_align(dacno: u8, phase: u8) -> Result<(), &'static str> {
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let mut margin_minus = None;
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let mut margin_plus = None;
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@ -218,7 +58,7 @@ fn sysref_dac_align(dacno: u8, phase: u16) -> Result<(), &'static str> {
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hmc7043::sysref_offset_dac(dacno, phase);
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ad9154::dac_sync(dacno)?;
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for d in 0..128 {
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for d in 0..24 {
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hmc7043::sysref_offset_dac(dacno, phase - d);
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let realign_occured = ad9154::dac_sync(dacno)?;
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if realign_occured {
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@ -229,7 +69,7 @@ fn sysref_dac_align(dacno: u8, phase: u16) -> Result<(), &'static str> {
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hmc7043::sysref_offset_dac(dacno, phase);
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ad9154::dac_sync(dacno)?;
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for d in 0..128 {
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for d in 0..24 {
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hmc7043::sysref_offset_dac(dacno, phase + d);
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let realign_occured = ad9154::dac_sync(dacno)?;
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if realign_occured {
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@ -242,7 +82,7 @@ fn sysref_dac_align(dacno: u8, phase: u16) -> Result<(), &'static str> {
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let margin_minus = margin_minus.unwrap();
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let margin_plus = margin_plus.unwrap();
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info!(" margins: -{} +{}", margin_minus, margin_plus);
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if margin_minus < 10 || margin_plus < 10 {
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if margin_minus < 5 || margin_plus < 5 {
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return Err("SYSREF margins at DAC are too small, board needs recalibration");
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}
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} else {
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@ -115,9 +115,12 @@ fn startup() {
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{
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board_artiq::ad9154::jesd_reset(false);
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board_artiq::ad9154::init();
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/*
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TODO:
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if let Err(e) = board_artiq::jesd204sync::sysref_auto_rtio_align() {
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error!("failed to align SYSREF at FPGA: {}", e);
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}
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*/
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if let Err(e) = board_artiq::jesd204sync::sysref_auto_dac_align() {
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error!("failed to align SYSREF at DAC: {}", e);
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}
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@ -489,9 +489,12 @@ pub extern fn main() -> i32 {
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info!("TSC loaded from uplink");
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#[cfg(has_ad9154)]
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{
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/*
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TODO:
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if let Err(e) = board_artiq::jesd204sync::sysref_auto_rtio_align() {
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error!("failed to align SYSREF at FPGA: {}", e);
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}
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*/
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if let Err(e) = board_artiq::jesd204sync::sysref_auto_dac_align() {
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error!("failed to align SYSREF at DAC: {}", e);
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}
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@ -91,22 +91,3 @@ class UltrascaleTX(Module, AutoCSR):
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self.submodules.control = JESD204BCoreTXControl(self.core)
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self.core.register_jsync(platform.request("dac_sync", dac))
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self.core.register_jref(jesd_crg.jref)
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# This assumes:
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# * coarse RTIO frequency = 16*SYSREF frequency
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# * JESD and coarse RTIO clocks are the same
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# (only reset may differ).
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# * SYSREF meets setup/hold at the FPGA when sampled
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# in the JESD/RTIO domain.
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#
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# Look at the 4 LSBs of the coarse RTIO timestamp counter
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# to determine SYSREF phase.
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class SysrefSampler(Module, AutoCSR):
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def __init__(self, coarse_ts, jref):
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self.sample_result = CSRStatus()
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sample = Signal()
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self.sync.jesd += If(coarse_ts[:4] == 0, sample.eq(jref))
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self.specials += MultiReg(sample, self.sample_result.status)
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@ -223,10 +223,6 @@ class Standalone(MiniSoC, AMPSoC, RTMCommon):
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self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
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self.rtio_tsc.coarse_ts, self.ad9154_crg.jref)
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self.csr_devices.append("sysref_sampler")
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class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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"""
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@ -395,10 +391,6 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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self.csr_devices.append("routing_table")
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self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
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self.rtio_tsc.coarse_ts, self.ad9154_crg.jref)
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self.csr_devices.append("sysref_sampler")
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def workaround_us_lvds_tristate(platform):
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# Those shoddy Kintex Ultrascale FPGAs take almost a microsecond to change the direction of a
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@ -684,10 +676,6 @@ class Satellite(BaseSoC, RTMCommon):
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
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self.rtio_tsc.coarse_ts, self.ad9154_crg.jref)
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self.csr_devices.append("sysref_sampler")
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rtio_clk_period = 1e9/rtio_clk_freq
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gth = self.drtio_transceiver.gths[0]
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platform.add_period_constraint(gth.txoutclk, rtio_clk_period/2)
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