From 4901cb9a8a75534290d3503b135dd9a038dac281 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Mon, 22 May 2017 17:46:55 +0200 Subject: [PATCH] sawg: fix clr width --- artiq/gateware/dsp/sawg.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/dsp/sawg.py b/artiq/gateware/dsp/sawg.py index 73eb29318..b7f4dd0b0 100644 --- a/artiq/gateware/dsp/sawg.py +++ b/artiq/gateware/dsp/sawg.py @@ -84,7 +84,7 @@ class SplineParallelDDS(SplineParallelDUC): class Config(Module): def __init__(self, width): - self.clr = Signal(4, reset=0b1111) + self.clr = Signal(3, reset=0b111) self.iq_en = Signal(2, reset=0b01) self.limits = [[Signal((width, True), reset=-(1 << width - 1)), Signal((width, True), reset=(1 << width - 1) - 1)]