mirror of https://github.com/m-labs/artiq.git
102 lines
3.3 KiB
Python
102 lines
3.3 KiB
Python
from migen import *
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from migen.genlib.cdc import PulseSynchronizer, MultiReg
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from misoc.interconnect.csr import *
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class DDMTDSamplerExtFF(Module):
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def __init__(self, ddmtd_inputs):
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# TODO: s/h timing at FPGA pads
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if hasattr(ddmtd_inputs, "rec_clk"):
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self.rec_clk = ddmtd_inputs.rec_clk
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else:
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self.rec_clk = Signal()
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self.specials += Instance("IBUFDS",
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i_I=ddmtd_inputs.rec_clk_p, i_IB=ddmtd_inputs.rec_clk_n,
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o_O=self.rec_clk)
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if hasattr(ddmtd_inputs, "main_xo"):
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self.main_xo = ddmtd_inputs.main_xo
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else:
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self.main_xo = Signal()
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self.specials += Instance("IBUFDS",
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i_I=ddmtd_inputs.main_xo_p, i_IB=ddmtd_inputs.main_xo_n,
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o_O=self.main_xo)
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class DDMTDSamplerGTP(Module):
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def __init__(self, gtp, main_xo_pads):
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self.rec_clk = Signal()
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self.main_xo = Signal()
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# Getting this signal from IBUFDS_GTE2 is problematic because:
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# 1. the clock gets divided by 2
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# 2. the transceiver PLL craps out if an improper clock signal is applied,
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# so we are disabling the buffer until the clock is stable.
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# 3. UG482 says "The O and ODIV2 outputs are not phase matched to each other",
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# which may or may not be a problem depending on what it actually means.
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main_xo_se = Signal()
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self.specials += Instance("IBUFDS",
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i_I=main_xo_pads.p, i_IB=main_xo_pads.n,
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o_O=main_xo_se)
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self.sync.helper += [
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self.rec_clk.eq(gtp.cd_rtio_rx0.clk),
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self.main_xo.eq(main_xo_se)
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]
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class DDMTDEdgeDetector(Module):
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def __init__(self, input_signal):
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self.rising = Signal()
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history = Signal(4)
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deglitched = Signal()
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self.sync.helper += history.eq(Cat(history[1:], input_signal))
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self.comb += deglitched.eq(input_signal | history[0] | history[1] | history[2] | history[3])
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deglitched_r = Signal()
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self.sync.helper += [
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deglitched_r.eq(deglitched),
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self.rising.eq(deglitched & ~deglitched_r)
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]
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class DDMTD(Module, AutoCSR):
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def __init__(self, counter, input_signal):
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self.arm = CSR()
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self.tag = CSRStatus(len(counter))
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# in helper clock domain
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self.h_tag = Signal(len(counter))
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self.h_tag_update = Signal()
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# # #
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ed = DDMTDEdgeDetector(input_signal)
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self.submodules += ed
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self.sync.helper += [
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self.h_tag_update.eq(0),
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If(ed.rising,
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self.h_tag_update.eq(1),
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self.h_tag.eq(counter)
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)
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]
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tag_update_ps = PulseSynchronizer("helper", "sys")
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self.submodules += tag_update_ps
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self.comb += tag_update_ps.i.eq(self.h_tag_update)
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tag_update = Signal()
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self.sync += tag_update.eq(tag_update_ps.o)
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tag = Signal(len(counter))
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self.h_tag.attr.add("no_retiming")
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self.specials += MultiReg(self.h_tag, tag)
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self.sync += [
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If(self.arm.re & self.arm.r, self.arm.w.eq(1)),
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If(tag_update,
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If(self.arm.w, self.tag.status.eq(tag)),
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self.arm.w.eq(0),
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)
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]
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