mirror of https://github.com/m-labs/artiq.git
gateware: connect CRI switch to kernel CPU.
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@ -102,6 +102,7 @@ class _NIST_Ions(MiniSoC, AMPSoC):
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mem_map = {
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"rtio": 0x20000000,
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"rtio_dma": 0x30000000,
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"cri_con": 0x50000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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@ -151,7 +152,7 @@ class _NIST_Ions(MiniSoC, AMPSoC):
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.csr_devices.append("cri_con")
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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