From 464202d0aad11f008d21bd9a6bb6da245ba85966 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 5 Apr 2017 16:10:53 +0000 Subject: [PATCH] gateware: connect CRI switch to kernel CPU. --- artiq/gateware/targets/kc705_dds.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/artiq/gateware/targets/kc705_dds.py b/artiq/gateware/targets/kc705_dds.py index dd9ba9cde..cc92d45a2 100755 --- a/artiq/gateware/targets/kc705_dds.py +++ b/artiq/gateware/targets/kc705_dds.py @@ -102,6 +102,7 @@ class _NIST_Ions(MiniSoC, AMPSoC): mem_map = { "rtio": 0x20000000, "rtio_dma": 0x30000000, + "cri_con": 0x50000000, "mailbox": 0x70000000 } mem_map.update(MiniSoC.mem_map) @@ -151,7 +152,7 @@ class _NIST_Ions(MiniSoC, AMPSoC): self.submodules.cri_con = rtio.CRIInterconnectShared( [self.rtio.cri, self.rtio_dma.cri], [self.rtio_core.cri]) - self.csr_devices.append("cri_con") + self.register_kernel_cpu_csrdevice("cri_con") self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj")