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remove DDS_AD9914 and DDS_ONEHOT_SEL
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parent
c2ba718efa
commit
455250b3f9
artiq
@ -53,7 +53,7 @@ fn worker(mut stream: TcpStream) -> io::Result<()> {
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sent_bytes: if wraparound { BUFFER_SIZE as u32 } else { total_byte_count as u32 },
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overflow_occurred: overflow_occurred,
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log_channel: csr::CONFIG_RTIO_LOG_CHANNEL as u8,
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dds_onehot_sel: csr::CONFIG_DDS_ONEHOT_SEL != 0
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dds_onehot_sel: true // kept for backward compatibility of analyzer dumps
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};
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trace!("{:?}", header);
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@ -224,8 +224,6 @@ class NIST_CLOCK(_NIST_Ions):
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_DDS_COUNT"] = 1
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self.config["DDS_CHANNELS_PER_BUS"] = 11
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self.config["DDS_AD9914"] = None
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self.config["DDS_ONEHOT_SEL"] = None
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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@ -301,8 +299,6 @@ class NIST_QC2(_NIST_Ions):
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_DDS_COUNT"] = 2
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self.config["DDS_CHANNELS_PER_BUS"] = 12
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self.config["DDS_AD9914"] = None
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self.config["DDS_ONEHOT_SEL"] = None
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for backplane_offset in range(2):
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phy = dds.AD9914(
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platform.request("dds", backplane_offset), 12, onehot=True)
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@ -235,8 +235,6 @@ class Phaser(MiniSoC, AMPSoC):
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_DDS_COUNT"] = 1
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self.config["DDS_CHANNELS_PER_BUS"] = 1
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self.config["DDS_AD9914"] = None
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self.config["DDS_ONEHOT_SEL"] = None
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self.submodules.rtio_crg = _PhaserCRG(
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platform, self.ad9154.jesd.cd_jesd.clk)
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