From 455250b3f93e1daeed35b6ce0fd6bafaf0126689 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 3 Jan 2017 22:04:25 +0100 Subject: [PATCH] remove DDS_AD9914 and DDS_ONEHOT_SEL --- artiq/firmware/runtime/analyzer.rs | 2 +- artiq/gateware/targets/kc705.py | 4 ---- artiq/gateware/targets/phaser.py | 2 -- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/artiq/firmware/runtime/analyzer.rs b/artiq/firmware/runtime/analyzer.rs index ea126512e..098866db0 100644 --- a/artiq/firmware/runtime/analyzer.rs +++ b/artiq/firmware/runtime/analyzer.rs @@ -53,7 +53,7 @@ fn worker(mut stream: TcpStream) -> io::Result<()> { sent_bytes: if wraparound { BUFFER_SIZE as u32 } else { total_byte_count as u32 }, overflow_occurred: overflow_occurred, log_channel: csr::CONFIG_RTIO_LOG_CHANNEL as u8, - dds_onehot_sel: csr::CONFIG_DDS_ONEHOT_SEL != 0 + dds_onehot_sel: true // kept for backward compatibility of analyzer dumps }; trace!("{:?}", header); diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index c88017349..16abb050a 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -224,8 +224,6 @@ class NIST_CLOCK(_NIST_Ions): self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels) self.config["RTIO_DDS_COUNT"] = 1 self.config["DDS_CHANNELS_PER_BUS"] = 11 - self.config["DDS_AD9914"] = None - self.config["DDS_ONEHOT_SEL"] = None phy = dds.AD9914(platform.request("dds"), 11, onehot=True) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, @@ -301,8 +299,6 @@ class NIST_QC2(_NIST_Ions): self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels) self.config["RTIO_DDS_COUNT"] = 2 self.config["DDS_CHANNELS_PER_BUS"] = 12 - self.config["DDS_AD9914"] = None - self.config["DDS_ONEHOT_SEL"] = None for backplane_offset in range(2): phy = dds.AD9914( platform.request("dds", backplane_offset), 12, onehot=True) diff --git a/artiq/gateware/targets/phaser.py b/artiq/gateware/targets/phaser.py index 2b4e2b97c..b5392f60a 100755 --- a/artiq/gateware/targets/phaser.py +++ b/artiq/gateware/targets/phaser.py @@ -235,8 +235,6 @@ class Phaser(MiniSoC, AMPSoC): self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels) self.config["RTIO_DDS_COUNT"] = 1 self.config["DDS_CHANNELS_PER_BUS"] = 1 - self.config["DDS_AD9914"] = None - self.config["DDS_ONEHOT_SEL"] = None self.submodules.rtio_crg = _PhaserCRG( platform, self.ad9154.jesd.cd_jesd.clk)