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artiq
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remove DDS_AD9914 and DDS_ONEHOT_SEL

This commit is contained in:
Sebastien Bourdeauducq 2017-01-03 22:04:25 +01:00
parent c2ba718efa
commit 455250b3f9
3 changed files with 1 additions and 7 deletions
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2
artiq/firmware/runtime/analyzer.rs
View File

@ -53,7 +53,7 @@ fn worker(mut stream: TcpStream) -> io::Result<()> {
sent_bytes: if wraparound { BUFFER_SIZE as u32 } else { total_byte_count as u32 }, sent_bytes: if wraparound { BUFFER_SIZE as u32 } else { total_byte_count as u32 },
overflow_occurred: overflow_occurred, overflow_occurred: overflow_occurred,
log_channel: csr::CONFIG_RTIO_LOG_CHANNEL as u8, log_channel: csr::CONFIG_RTIO_LOG_CHANNEL as u8,
dds_onehot_sel: csr::CONFIG_DDS_ONEHOT_SEL != 0 dds_onehot_sel: true // kept for backward compatibility of analyzer dumps
}; };
trace!("{:?}", header); trace!("{:?}", header);

4
artiq/gateware/targets/kc705.py
View File

@ -224,8 +224,6 @@ class NIST_CLOCK(_NIST_Ions):
self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels) self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
self.config["RTIO_DDS_COUNT"] = 1 self.config["RTIO_DDS_COUNT"] = 1
self.config["DDS_CHANNELS_PER_BUS"] = 11 self.config["DDS_CHANNELS_PER_BUS"] = 11
self.config["DDS_AD9914"] = None
self.config["DDS_ONEHOT_SEL"] = None
phy = dds.AD9914(platform.request("dds"), 11, onehot=True) phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, rtio_channels.append(rtio.Channel.from_phy(phy,
@ -301,8 +299,6 @@ class NIST_QC2(_NIST_Ions):
self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels) self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
self.config["RTIO_DDS_COUNT"] = 2 self.config["RTIO_DDS_COUNT"] = 2
self.config["DDS_CHANNELS_PER_BUS"] = 12 self.config["DDS_CHANNELS_PER_BUS"] = 12
self.config["DDS_AD9914"] = None
self.config["DDS_ONEHOT_SEL"] = None
for backplane_offset in range(2): for backplane_offset in range(2):
phy = dds.AD9914( phy = dds.AD9914(
platform.request("dds", backplane_offset), 12, onehot=True) platform.request("dds", backplane_offset), 12, onehot=True)

2
artiq/gateware/targets/phaser.py
View File

@ -235,8 +235,6 @@ class Phaser(MiniSoC, AMPSoC):
self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels) self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
self.config["RTIO_DDS_COUNT"] = 1 self.config["RTIO_DDS_COUNT"] = 1
self.config["DDS_CHANNELS_PER_BUS"] = 1 self.config["DDS_CHANNELS_PER_BUS"] = 1
self.config["DDS_AD9914"] = None
self.config["DDS_ONEHOT_SEL"] = None
self.submodules.rtio_crg = _PhaserCRG( self.submodules.rtio_crg = _PhaserCRG(
platform, self.ad9154.jesd.cd_jesd.clk) platform, self.ad9154.jesd.cd_jesd.clk)