M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq
2
0
Fork 1
Code Issues Projects Releases Wiki Activity

satman: update for changes in firmware elsewhere.

pull/882/merge
whitequark 2017-12-28 07:10:34 +00:00
parent d3066e5044
commit 3b18ece3b7
6 changed files with 68 additions and 76 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
artiq/firmware/Cargo.lock generated
View File

@ -216,6 +216,7 @@ version = "0.0.0"
dependencies = [
"alloc_list 0.0.0",
"board 0.0.0",
"board_artiq 0.0.0",
"build_artiq 0.0.0",
"compiler_builtins 0.1.0 (git+https://github.com/rust-lang-nursery/compiler-builtins?rev=631b568)",
"drtioaux 0.0.0",

1
artiq/firmware/runtime/lib.rs
View File

@ -230,7 +230,6 @@ pub extern fn exception(vect: u32, _regs: *const u32, pc: u32, ea: u32) {
#[no_mangle]
pub extern fn abort() {
println!("aborted");
loop {}
}

5
artiq/firmware/satman/Cargo.toml
View File

@ -13,12 +13,13 @@ path = "lib.rs"
build_artiq = { path = "../libbuild_artiq" }
[dependencies]
log = { version = "0.3", default-features = false }
alloc_list = { path = "../liballoc_list" }
board = { path = "../libboard", features = ["uart_console"] }
board_artiq = { path = "../libboard_artiq" }
std_artiq = { path = "../libstd_artiq", features = ["alloc"] }
logger_artiq = { path = "../liblogger_artiq" }
board = { path = "../libboard", features = ["uart_console"] }
drtioaux = { path = "../libdrtioaux" }
log = { version = "0.3", default-features = false }
[dependencies.compiler_builtins]
git = "https://github.com/rust-lang-nursery/compiler-builtins"

85
artiq/firmware/satman/lib.rs
View File

@ -9,8 +9,16 @@ extern crate log;
extern crate logger_artiq;
#[macro_use]
extern crate board;
extern crate board_artiq;
extern crate drtioaux;
use board::csr;
use board_artiq::{i2c, spi, si5324};
#[cfg(has_serwb_phy_amc)]
use board_artiq::serwb;
#[cfg(has_hmc830_7043)]
use board_artiq::hmc830_7043;
fn process_aux_packet(p: &drtioaux::Packet) {
// In the code below, *_chan_sel_write takes an u8 if there are fewer than 256 channels,
// and u16 otherwise; hence the `as _` conversion.
@ -20,16 +28,16 @@ fn process_aux_packet(p: &drtioaux::Packet) {
drtioaux::Packet::RtioErrorRequest => {
let errors;
unsafe {
errors = (board::csr::DRTIO[0].rtio_error_read)();
errors = (csr::DRTIO[0].rtio_error_read)();
}
if errors & 1 != 0 {
unsafe {
(board::csr::DRTIO[0].rtio_error_write)(1);
(csr::DRTIO[0].rtio_error_write)(1);
}
drtioaux::hw::send_link(0, &drtioaux::Packet::RtioErrorCollisionReply).unwrap();
} else if errors & 2 != 0 {
unsafe {
(board::csr::DRTIO[0].rtio_error_write)(2);
(csr::DRTIO[0].rtio_error_write)(2);
}
drtioaux::hw::send_link(0, &drtioaux::Packet::RtioErrorBusyReply).unwrap();
} else {
@ -41,10 +49,10 @@ fn process_aux_packet(p: &drtioaux::Packet) {
let value;
#[cfg(has_rtio_moninj)]
unsafe {
board::csr::rtio_moninj::mon_chan_sel_write(channel as _);
board::csr::rtio_moninj::mon_probe_sel_write(probe);
board::csr::rtio_moninj::mon_value_update_write(1);
value = board::csr::rtio_moninj::mon_value_read();
csr::rtio_moninj::mon_chan_sel_write(channel as _);
csr::rtio_moninj::mon_probe_sel_write(probe);
csr::rtio_moninj::mon_value_update_write(1);
value = csr::rtio_moninj::mon_value_read();
}
#[cfg(not(has_rtio_moninj))]
{
@ -56,18 +64,18 @@ fn process_aux_packet(p: &drtioaux::Packet) {
drtioaux::Packet::InjectionRequest { channel, overrd, value } => {
#[cfg(has_rtio_moninj)]
unsafe {
board::csr::rtio_moninj::inj_chan_sel_write(channel as _);
board::csr::rtio_moninj::inj_override_sel_write(overrd);
board::csr::rtio_moninj::inj_value_write(value);
csr::rtio_moninj::inj_chan_sel_write(channel as _);
csr::rtio_moninj::inj_override_sel_write(overrd);
csr::rtio_moninj::inj_value_write(value);
}
},
drtioaux::Packet::InjectionStatusRequest { channel, overrd } => {
let value;
#[cfg(has_rtio_moninj)]
unsafe {
board::csr::rtio_moninj::inj_chan_sel_write(channel as _);
board::csr::rtio_moninj::inj_override_sel_write(overrd);
value = board::csr::rtio_moninj::inj_value_read();
csr::rtio_moninj::inj_chan_sel_write(channel as _);
csr::rtio_moninj::inj_override_sel_write(overrd);
value = csr::rtio_moninj::inj_value_read();
}
#[cfg(not(has_rtio_moninj))]
{
@ -78,44 +86,44 @@ fn process_aux_packet(p: &drtioaux::Packet) {
},
drtioaux::Packet::I2cStartRequest { busno } => {
let succeeded = board::i2c::start(busno).is_ok();
let succeeded = i2c::start(busno).is_ok();
drtioaux::hw::send_link(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded }).unwrap();
}
drtioaux::Packet::I2cRestartRequest { busno } => {
let succeeded = board::i2c::restart(busno).is_ok();
let succeeded = i2c::restart(busno).is_ok();
drtioaux::hw::send_link(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded }).unwrap();
}
drtioaux::Packet::I2cStopRequest { busno } => {
let succeeded = board::i2c::stop(busno).is_ok();
let succeeded = i2c::stop(busno).is_ok();
drtioaux::hw::send_link(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded }).unwrap();
}
drtioaux::Packet::I2cWriteRequest { busno, data } => {
match board::i2c::write(busno, data) {
match i2c::write(busno, data) {
Ok(ack) => drtioaux::hw::send_link(0, &drtioaux::Packet::I2cWriteReply { succeeded: true, ack: ack }).unwrap(),
Err(_) => drtioaux::hw::send_link(0, &drtioaux::Packet::I2cWriteReply { succeeded: false, ack: false }).unwrap()
};
}
drtioaux::Packet::I2cReadRequest { busno, ack } => {
match board::i2c::read(busno, ack) {
match i2c::read(busno, ack) {
Ok(data) => drtioaux::hw::send_link(0, &drtioaux::Packet::I2cReadReply { succeeded: true, data: data }).unwrap(),
Err(_) => drtioaux::hw::send_link(0, &drtioaux::Packet::I2cReadReply { succeeded: false, data: 0xff }).unwrap()
};
}
drtioaux::Packet::SpiSetConfigRequest { busno, flags, write_div, read_div } => {
let succeeded = board::spi::set_config(busno, flags, write_div, read_div).is_ok();
let succeeded = spi::set_config(busno, flags, write_div, read_div).is_ok();
drtioaux::hw::send_link(0, &drtioaux::Packet::SpiBasicReply { succeeded: succeeded }).unwrap();
},
drtioaux::Packet::SpiSetXferRequest { busno, chip_select, write_length, read_length } => {
let succeeded = board::spi::set_xfer(busno, chip_select, write_length, read_length).is_ok();
let succeeded = spi::set_xfer(busno, chip_select, write_length, read_length).is_ok();
drtioaux::hw::send_link(0, &drtioaux::Packet::SpiBasicReply { succeeded: succeeded }).unwrap();
}
drtioaux::Packet::SpiWriteRequest { busno, data } => {
let succeeded = board::spi::write(busno, data).is_ok();
let succeeded = spi::write(busno, data).is_ok();
drtioaux::hw::send_link(0, &drtioaux::Packet::SpiBasicReply { succeeded: succeeded }).unwrap();
}
drtioaux::Packet::SpiReadRequest { busno } => {
match board::spi::read(busno) {
match spi::read(busno) {
Ok(data) => drtioaux::hw::send_link(0, &drtioaux::Packet::SpiReadReply { succeeded: true, data: data }).unwrap(),
Err(_) => drtioaux::hw::send_link(0, &drtioaux::Packet::SpiReadReply { succeeded: false, data: 0 }).unwrap()
};
@ -138,8 +146,8 @@ fn process_aux_packets() {
fn process_errors() {
let errors;
unsafe {
errors = (board::csr::DRTIO[0].protocol_error_read)();
(board::csr::DRTIO[0].protocol_error_write)(errors);
errors = (csr::DRTIO[0].protocol_error_read)();
(csr::DRTIO[0].protocol_error_write)(errors);
}
if errors & 1 != 0 {
error!("received packet of an unknown type");
@ -160,8 +168,8 @@ fn process_errors() {
#[cfg(rtio_frequency = "62.5")]
const SI5324_SETTINGS: board::si5324::FrequencySettings
= board::si5324::FrequencySettings {
const SI5324_SETTINGS: si5324::FrequencySettings
= si5324::FrequencySettings {
n1_hs : 10,
nc1_ls : 8,
n2_hs : 10,
@ -172,8 +180,8 @@ const SI5324_SETTINGS: board::si5324::FrequencySettings
};
#[cfg(rtio_frequency = "150.0")]
const SI5324_SETTINGS: board::si5324::FrequencySettings
= board::si5324::FrequencySettings {
const SI5324_SETTINGS: si5324::FrequencySettings
= si5324::FrequencySettings {
n1_hs : 9,
nc1_ls : 4,
n2_hs : 10,
@ -185,7 +193,7 @@ const SI5324_SETTINGS: board::si5324::FrequencySettings
fn drtio_link_is_up() -> bool {
unsafe {
(board::csr::DRTIO[0].link_status_read)() == 1
(csr::DRTIO[0].link_status_read)() == 1
}
}
@ -193,28 +201,28 @@ fn startup() {
board::clock::init();
info!("ARTIQ satellite manager starting...");
info!("software version {}", include_str!(concat!(env!("OUT_DIR"), "/git-describe")));
info!("gateware version {}", board::ident(&mut [0; 64]));
info!("gateware version {}", board::ident::read(&mut [0; 64]));
#[cfg(has_serwb_phy_amc)]
board::serwb::wait_init();
serwb::wait_init();
#[cfg(has_hmc830_7043)]
board::hmc830_7043::init().expect("cannot initialize HMC830/7043");
board::i2c::init();
board::si5324::setup(&SI5324_SETTINGS).expect("cannot initialize Si5324");
hmc830_7043::init().expect("cannot initialize HMC830/7043");
i2c::init();
si5324::setup(&SI5324_SETTINGS).expect("cannot initialize Si5324");
loop {
while !drtio_link_is_up() {
process_errors();
}
info!("link is up, switching to recovered clock");
board::si5324::select_ext_input(true).expect("failed to switch clocks");
si5324::select_ext_input(true).expect("failed to switch clocks");
while drtio_link_is_up() {
process_errors();
process_aux_packets();
}
info!("link is down, switching to local crystal clock");
board::si5324::select_ext_input(false).expect("failed to switch clocks");
si5324::select_ext_input(false).expect("failed to switch clocks");
}
}
@ -237,13 +245,14 @@ pub extern fn main() -> i32 {
}
#[no_mangle]
pub extern fn exception_handler(vect: u32, _regs: *const u32, pc: u32, ea: u32) {
pub extern fn exception(vect: u32, _regs: *const u32, pc: u32, ea: u32) {
panic!("exception {:?} at PC 0x{:x}, EA 0x{:x}", vect, pc, ea)
}
#[no_mangle]
pub extern fn abort() {
panic!("aborted")
println!("aborted");
loop {}
}
#[no_mangle]

45
artiq/firmware/satman/satman.ld
View File

@ -1,22 +1,23 @@
INCLUDE generated/output_format.ld
STARTUP(crt0-or1k.o)
ENTRY(_start)
INCLUDE generated/regions.ld
ENTRY(_reset_handler)
SECTIONS
{
.vectors :
{
*(.vectors)
} > main_ram
.text :
{
_ftext = .;
*(.text .stub .text.* .gnu.linkonce.t.*)
_etext = .;
*(.text .text.*)
} > main_ram
/* https://sourceware.org/bugzilla/show_bug.cgi?id=20475 */
.got :
{
_GLOBAL_OFFSET_TABLE_ = .;
PROVIDE(_GLOBAL_OFFSET_TABLE_ = .);
*(.got)
} > main_ram
@ -27,40 +28,26 @@ SECTIONS
.rodata :
{
. = ALIGN(4);
_frodata = .;
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
*(.rodata .rodata.*)
_erodata = .;
} > main_ram
.data :
{
. = ALIGN(4);
_fdata = .;
*(.data .data.* .gnu.linkonce.d.*)
*(.data1)
*(.sdata .sdata.* .gnu.linkonce.s.*)
_edata = .;
*(.data .data.*)
} > main_ram
.bss :
.bss ALIGN(4) :
{
. = ALIGN(4);
_fbss = .;
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
*(.bss .bss.*)
. = ALIGN(4);
_ebss = .;
} > main_ram
.stack :
.stack ALIGN(0x1000) :
{
. = ALIGN(0x1000);
_estack = .;
. += 0x4000;
_fstack = . - 4;
@ -72,10 +59,4 @@ SECTIONS
. = ORIGIN(main_ram) + LENGTH(main_ram);
_eheap = .;
} > main_ram
/DISCARD/ :
{
*(.eh_frame)
*(.gcc_except_table)
}
}

7
artiq/frontend/artiq_devtool.py
View File

@ -39,7 +39,8 @@ def get_argparser():
parser.add_argument("-t", "--target", metavar="TARGET",
type=str, default="kc705_dds",
help="Target to build, one of: "
"kc705_dds kc705_drtio_master kc705_drtio_satellite")
"kc705_dds sayma_amc_standalone "
"sayma_amc_drtio_master sayma_amc_drtio_satellite")
parser.add_argument("actions", metavar="ACTION",
type=str, default=[], nargs="+",
@ -55,9 +56,9 @@ def main():
if args.verbose == args.quiet == 0:
logging.getLogger().setLevel(logging.INFO)
if args.target == "kc705_dds" or args.target == "kc705_drtio_master":
if args.target in ["kc705_dds", "sayma_amc_standalone", "sayma_amc_drtio_master"]:
firmware = "runtime"
elif args.target == "kc705_drtio_satellite":
elif args.target == "sayma_amc_drtio_satellite":
firmware = "satman"
else:
raise NotImplementedError("unknown target {}".format(args.target))