mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-25 03:08:27 +08:00
satman: update for changes in firmware elsewhere.
This commit is contained in:
parent
d3066e5044
commit
3b18ece3b7
1
artiq/firmware/Cargo.lock
generated
1
artiq/firmware/Cargo.lock
generated
@ -216,6 +216,7 @@ version = "0.0.0"
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dependencies = [
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"alloc_list 0.0.0",
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"board 0.0.0",
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"board_artiq 0.0.0",
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"build_artiq 0.0.0",
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"compiler_builtins 0.1.0 (git+https://github.com/rust-lang-nursery/compiler-builtins?rev=631b568)",
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"drtioaux 0.0.0",
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@ -230,7 +230,6 @@ pub extern fn exception(vect: u32, _regs: *const u32, pc: u32, ea: u32) {
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#[no_mangle]
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pub extern fn abort() {
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println!("aborted");
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loop {}
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}
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@ -13,12 +13,13 @@ path = "lib.rs"
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build_artiq = { path = "../libbuild_artiq" }
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[dependencies]
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log = { version = "0.3", default-features = false }
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alloc_list = { path = "../liballoc_list" }
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board = { path = "../libboard", features = ["uart_console"] }
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board_artiq = { path = "../libboard_artiq" }
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std_artiq = { path = "../libstd_artiq", features = ["alloc"] }
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logger_artiq = { path = "../liblogger_artiq" }
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board = { path = "../libboard", features = ["uart_console"] }
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drtioaux = { path = "../libdrtioaux" }
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log = { version = "0.3", default-features = false }
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[dependencies.compiler_builtins]
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git = "https://github.com/rust-lang-nursery/compiler-builtins"
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@ -9,8 +9,16 @@ extern crate log;
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extern crate logger_artiq;
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#[macro_use]
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extern crate board;
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extern crate board_artiq;
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extern crate drtioaux;
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use board::csr;
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use board_artiq::{i2c, spi, si5324};
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#[cfg(has_serwb_phy_amc)]
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use board_artiq::serwb;
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#[cfg(has_hmc830_7043)]
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use board_artiq::hmc830_7043;
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fn process_aux_packet(p: &drtioaux::Packet) {
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// In the code below, *_chan_sel_write takes an u8 if there are fewer than 256 channels,
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// and u16 otherwise; hence the `as _` conversion.
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@ -20,16 +28,16 @@ fn process_aux_packet(p: &drtioaux::Packet) {
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drtioaux::Packet::RtioErrorRequest => {
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let errors;
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unsafe {
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errors = (board::csr::DRTIO[0].rtio_error_read)();
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errors = (csr::DRTIO[0].rtio_error_read)();
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}
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if errors & 1 != 0 {
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unsafe {
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(board::csr::DRTIO[0].rtio_error_write)(1);
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(csr::DRTIO[0].rtio_error_write)(1);
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}
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drtioaux::hw::send_link(0, &drtioaux::Packet::RtioErrorCollisionReply).unwrap();
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} else if errors & 2 != 0 {
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unsafe {
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(board::csr::DRTIO[0].rtio_error_write)(2);
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(csr::DRTIO[0].rtio_error_write)(2);
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}
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drtioaux::hw::send_link(0, &drtioaux::Packet::RtioErrorBusyReply).unwrap();
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} else {
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@ -41,10 +49,10 @@ fn process_aux_packet(p: &drtioaux::Packet) {
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let value;
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#[cfg(has_rtio_moninj)]
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unsafe {
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board::csr::rtio_moninj::mon_chan_sel_write(channel as _);
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board::csr::rtio_moninj::mon_probe_sel_write(probe);
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board::csr::rtio_moninj::mon_value_update_write(1);
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value = board::csr::rtio_moninj::mon_value_read();
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csr::rtio_moninj::mon_chan_sel_write(channel as _);
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csr::rtio_moninj::mon_probe_sel_write(probe);
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csr::rtio_moninj::mon_value_update_write(1);
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value = csr::rtio_moninj::mon_value_read();
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}
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#[cfg(not(has_rtio_moninj))]
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{
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@ -56,18 +64,18 @@ fn process_aux_packet(p: &drtioaux::Packet) {
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drtioaux::Packet::InjectionRequest { channel, overrd, value } => {
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#[cfg(has_rtio_moninj)]
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unsafe {
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board::csr::rtio_moninj::inj_chan_sel_write(channel as _);
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board::csr::rtio_moninj::inj_override_sel_write(overrd);
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board::csr::rtio_moninj::inj_value_write(value);
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csr::rtio_moninj::inj_chan_sel_write(channel as _);
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csr::rtio_moninj::inj_override_sel_write(overrd);
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csr::rtio_moninj::inj_value_write(value);
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}
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},
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drtioaux::Packet::InjectionStatusRequest { channel, overrd } => {
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let value;
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#[cfg(has_rtio_moninj)]
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unsafe {
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board::csr::rtio_moninj::inj_chan_sel_write(channel as _);
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board::csr::rtio_moninj::inj_override_sel_write(overrd);
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value = board::csr::rtio_moninj::inj_value_read();
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csr::rtio_moninj::inj_chan_sel_write(channel as _);
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csr::rtio_moninj::inj_override_sel_write(overrd);
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value = csr::rtio_moninj::inj_value_read();
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}
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#[cfg(not(has_rtio_moninj))]
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{
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@ -78,44 +86,44 @@ fn process_aux_packet(p: &drtioaux::Packet) {
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},
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drtioaux::Packet::I2cStartRequest { busno } => {
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let succeeded = board::i2c::start(busno).is_ok();
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let succeeded = i2c::start(busno).is_ok();
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drtioaux::hw::send_link(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded }).unwrap();
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}
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drtioaux::Packet::I2cRestartRequest { busno } => {
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let succeeded = board::i2c::restart(busno).is_ok();
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let succeeded = i2c::restart(busno).is_ok();
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drtioaux::hw::send_link(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded }).unwrap();
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}
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drtioaux::Packet::I2cStopRequest { busno } => {
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let succeeded = board::i2c::stop(busno).is_ok();
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let succeeded = i2c::stop(busno).is_ok();
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drtioaux::hw::send_link(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded }).unwrap();
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}
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drtioaux::Packet::I2cWriteRequest { busno, data } => {
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match board::i2c::write(busno, data) {
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match i2c::write(busno, data) {
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Ok(ack) => drtioaux::hw::send_link(0, &drtioaux::Packet::I2cWriteReply { succeeded: true, ack: ack }).unwrap(),
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Err(_) => drtioaux::hw::send_link(0, &drtioaux::Packet::I2cWriteReply { succeeded: false, ack: false }).unwrap()
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};
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}
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drtioaux::Packet::I2cReadRequest { busno, ack } => {
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match board::i2c::read(busno, ack) {
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match i2c::read(busno, ack) {
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Ok(data) => drtioaux::hw::send_link(0, &drtioaux::Packet::I2cReadReply { succeeded: true, data: data }).unwrap(),
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Err(_) => drtioaux::hw::send_link(0, &drtioaux::Packet::I2cReadReply { succeeded: false, data: 0xff }).unwrap()
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};
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}
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drtioaux::Packet::SpiSetConfigRequest { busno, flags, write_div, read_div } => {
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let succeeded = board::spi::set_config(busno, flags, write_div, read_div).is_ok();
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let succeeded = spi::set_config(busno, flags, write_div, read_div).is_ok();
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drtioaux::hw::send_link(0, &drtioaux::Packet::SpiBasicReply { succeeded: succeeded }).unwrap();
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},
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drtioaux::Packet::SpiSetXferRequest { busno, chip_select, write_length, read_length } => {
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let succeeded = board::spi::set_xfer(busno, chip_select, write_length, read_length).is_ok();
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let succeeded = spi::set_xfer(busno, chip_select, write_length, read_length).is_ok();
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drtioaux::hw::send_link(0, &drtioaux::Packet::SpiBasicReply { succeeded: succeeded }).unwrap();
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}
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drtioaux::Packet::SpiWriteRequest { busno, data } => {
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let succeeded = board::spi::write(busno, data).is_ok();
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let succeeded = spi::write(busno, data).is_ok();
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drtioaux::hw::send_link(0, &drtioaux::Packet::SpiBasicReply { succeeded: succeeded }).unwrap();
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}
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drtioaux::Packet::SpiReadRequest { busno } => {
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match board::spi::read(busno) {
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match spi::read(busno) {
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Ok(data) => drtioaux::hw::send_link(0, &drtioaux::Packet::SpiReadReply { succeeded: true, data: data }).unwrap(),
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Err(_) => drtioaux::hw::send_link(0, &drtioaux::Packet::SpiReadReply { succeeded: false, data: 0 }).unwrap()
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};
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@ -138,8 +146,8 @@ fn process_aux_packets() {
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fn process_errors() {
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let errors;
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unsafe {
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errors = (board::csr::DRTIO[0].protocol_error_read)();
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(board::csr::DRTIO[0].protocol_error_write)(errors);
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errors = (csr::DRTIO[0].protocol_error_read)();
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(csr::DRTIO[0].protocol_error_write)(errors);
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}
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if errors & 1 != 0 {
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error!("received packet of an unknown type");
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@ -160,8 +168,8 @@ fn process_errors() {
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#[cfg(rtio_frequency = "62.5")]
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const SI5324_SETTINGS: board::si5324::FrequencySettings
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= board::si5324::FrequencySettings {
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 8,
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n2_hs : 10,
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@ -172,8 +180,8 @@ const SI5324_SETTINGS: board::si5324::FrequencySettings
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};
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#[cfg(rtio_frequency = "150.0")]
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const SI5324_SETTINGS: board::si5324::FrequencySettings
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= board::si5324::FrequencySettings {
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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n1_hs : 9,
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nc1_ls : 4,
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n2_hs : 10,
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@ -185,7 +193,7 @@ const SI5324_SETTINGS: board::si5324::FrequencySettings
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fn drtio_link_is_up() -> bool {
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unsafe {
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(board::csr::DRTIO[0].link_status_read)() == 1
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(csr::DRTIO[0].link_status_read)() == 1
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}
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}
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@ -193,28 +201,28 @@ fn startup() {
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board::clock::init();
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info!("ARTIQ satellite manager starting...");
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info!("software version {}", include_str!(concat!(env!("OUT_DIR"), "/git-describe")));
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info!("gateware version {}", board::ident(&mut [0; 64]));
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info!("gateware version {}", board::ident::read(&mut [0; 64]));
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#[cfg(has_serwb_phy_amc)]
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board::serwb::wait_init();
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serwb::wait_init();
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#[cfg(has_hmc830_7043)]
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board::hmc830_7043::init().expect("cannot initialize HMC830/7043");
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board::i2c::init();
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board::si5324::setup(&SI5324_SETTINGS).expect("cannot initialize Si5324");
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hmc830_7043::init().expect("cannot initialize HMC830/7043");
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i2c::init();
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si5324::setup(&SI5324_SETTINGS).expect("cannot initialize Si5324");
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loop {
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while !drtio_link_is_up() {
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process_errors();
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}
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info!("link is up, switching to recovered clock");
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board::si5324::select_ext_input(true).expect("failed to switch clocks");
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si5324::select_ext_input(true).expect("failed to switch clocks");
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while drtio_link_is_up() {
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process_errors();
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process_aux_packets();
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}
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info!("link is down, switching to local crystal clock");
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board::si5324::select_ext_input(false).expect("failed to switch clocks");
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si5324::select_ext_input(false).expect("failed to switch clocks");
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}
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}
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@ -237,13 +245,14 @@ pub extern fn main() -> i32 {
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}
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#[no_mangle]
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pub extern fn exception_handler(vect: u32, _regs: *const u32, pc: u32, ea: u32) {
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pub extern fn exception(vect: u32, _regs: *const u32, pc: u32, ea: u32) {
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panic!("exception {:?} at PC 0x{:x}, EA 0x{:x}", vect, pc, ea)
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}
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#[no_mangle]
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pub extern fn abort() {
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panic!("aborted")
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println!("aborted");
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loop {}
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}
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#[no_mangle]
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@ -1,22 +1,23 @@
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INCLUDE generated/output_format.ld
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STARTUP(crt0-or1k.o)
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ENTRY(_start)
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INCLUDE generated/regions.ld
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ENTRY(_reset_handler)
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SECTIONS
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{
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.vectors :
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{
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*(.vectors)
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} > main_ram
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.text :
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{
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_ftext = .;
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*(.text .stub .text.* .gnu.linkonce.t.*)
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_etext = .;
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*(.text .text.*)
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} > main_ram
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/* https://sourceware.org/bugzilla/show_bug.cgi?id=20475 */
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.got :
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{
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_GLOBAL_OFFSET_TABLE_ = .;
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PROVIDE(_GLOBAL_OFFSET_TABLE_ = .);
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*(.got)
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} > main_ram
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@ -27,40 +28,26 @@ SECTIONS
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.rodata :
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{
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. = ALIGN(4);
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_frodata = .;
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*(.rodata .rodata.* .gnu.linkonce.r.*)
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*(.rodata1)
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*(.rodata .rodata.*)
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_erodata = .;
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} > main_ram
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.data :
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{
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. = ALIGN(4);
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_fdata = .;
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*(.data .data.* .gnu.linkonce.d.*)
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*(.data1)
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*(.sdata .sdata.* .gnu.linkonce.s.*)
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_edata = .;
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*(.data .data.*)
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} > main_ram
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.bss :
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.bss ALIGN(4) :
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{
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. = ALIGN(4);
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_fbss = .;
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*(.dynsbss)
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*(.sbss .sbss.* .gnu.linkonce.sb.*)
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*(.scommon)
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*(.dynbss)
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*(.bss .bss.* .gnu.linkonce.b.*)
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*(COMMON)
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*(.bss .bss.*)
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. = ALIGN(4);
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_ebss = .;
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} > main_ram
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.stack :
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.stack ALIGN(0x1000) :
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{
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. = ALIGN(0x1000);
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_estack = .;
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. += 0x4000;
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_fstack = . - 4;
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@ -72,10 +59,4 @@ SECTIONS
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. = ORIGIN(main_ram) + LENGTH(main_ram);
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_eheap = .;
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} > main_ram
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/DISCARD/ :
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{
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*(.eh_frame)
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*(.gcc_except_table)
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}
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}
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@ -39,7 +39,8 @@ def get_argparser():
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parser.add_argument("-t", "--target", metavar="TARGET",
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type=str, default="kc705_dds",
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help="Target to build, one of: "
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"kc705_dds kc705_drtio_master kc705_drtio_satellite")
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"kc705_dds sayma_amc_standalone "
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"sayma_amc_drtio_master sayma_amc_drtio_satellite")
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parser.add_argument("actions", metavar="ACTION",
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type=str, default=[], nargs="+",
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@ -55,9 +56,9 @@ def main():
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if args.verbose == args.quiet == 0:
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logging.getLogger().setLevel(logging.INFO)
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if args.target == "kc705_dds" or args.target == "kc705_drtio_master":
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if args.target in ["kc705_dds", "sayma_amc_standalone", "sayma_amc_drtio_master"]:
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firmware = "runtime"
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elif args.target == "kc705_drtio_satellite":
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elif args.target == "sayma_amc_drtio_satellite":
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firmware = "satman"
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else:
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raise NotImplementedError("unknown target {}".format(args.target))
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