mirror of https://github.com/m-labs/artiq.git
suservo: fix clkout cd drive
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f74998a5e0
commit
3942c2d274
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@ -544,7 +544,8 @@ class SUServo(_StandaloneBase):
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clkout = Signal()
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clkout = Signal()
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clkout_fabric = Signal()
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clkout_fabric = Signal()
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self.specials += [
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self.specials += [
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DifferentialInput(pads.clkout_p, pads.clkout_n, clkout),
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DifferentialInput(
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sampler_pads.clkout_p, sampler_pads.clkout_n, clkout),
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Instance("BUFH", i_I=clkout, o_O=clkout_fabric),
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Instance("BUFH", i_I=clkout, o_O=clkout_fabric),
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Instance("BUFIO", i_I=clkout, o_O=su.adc.clkout_io)
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Instance("BUFIO", i_I=clkout, o_O=su.adc.clkout_io)
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]
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]
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@ -602,12 +603,12 @@ class SUServo(_StandaloneBase):
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self.add_rtio(rtio_channels)
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self.add_rtio(rtio_channels)
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platform.add_period_constraint(su.adc.cd_ret.clk, 8.)
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platform.add_period_constraint(self.cd_ret.clk, 8.)
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platform.add_false_path_constraints(
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platform.add_false_path_constraints(
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su.adc.cd_ret.clk,
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self.cd_ret.clk,
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self.rtio_crg.cd_rtio.clk)
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self.rtio_crg.cd_rtio.clk)
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platform.add_false_path_constraints(
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platform.add_false_path_constraints(
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su.adc.cd_ret.clk,
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self.cd_ret.clk,
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self.crg.cd_sys.clk)
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self.crg.cd_sys.clk)
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