rtio: fix DMA TimeOffset stream.connect

2016-12-01 16:43:46 +08:00 · 2016-12-01 16:43:46 +08:00 · 3931d8097b
parent d4cb1eb998
commit 3931d8097b
1 changed files with 2 additions and 2 deletions
--- a/artiq/gateware/rtio/dma.py
+++ b/artiq/gateware/rtio/dma.py
@ -194,7 +194,7 @@ class TimeOffset(Module, AutoCSR):
        pipe_ce = Signal()
        self.sync += \
            If(pipe_ce,
-                self.source.payload.connect(self.sink.payload,
+                self.sink.payload.connect(self.source.payload,
                                          leave_out={"timestamp"}),
                self.source.payload.timestamp.eq(self.sink.payload.timestamp
                                                 + self.time_offset.storage),