mirror of https://github.com/m-labs/artiq.git
rtio: fix DMA TimeOffset stream.connect
This commit is contained in:
parent
d4cb1eb998
commit
3931d8097b
|
@ -194,8 +194,8 @@ class TimeOffset(Module, AutoCSR):
|
||||||
pipe_ce = Signal()
|
pipe_ce = Signal()
|
||||||
self.sync += \
|
self.sync += \
|
||||||
If(pipe_ce,
|
If(pipe_ce,
|
||||||
self.source.payload.connect(self.sink.payload,
|
self.sink.payload.connect(self.source.payload,
|
||||||
leave_out={"timestamp"}),
|
leave_out={"timestamp"}),
|
||||||
self.source.payload.timestamp.eq(self.sink.payload.timestamp
|
self.source.payload.timestamp.eq(self.sink.payload.timestamp
|
||||||
+ self.time_offset.storage),
|
+ self.time_offset.storage),
|
||||||
self.source.stb.eq(self.sink.stb)
|
self.source.stb.eq(self.sink.stb)
|
||||||
|
|
Loading…
Reference in New Issue