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artiq
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fix type, clean clear

This commit is contained in:
Robert Jördens 2022-09-02 19:47:06 +00:00
parent b9727fdfce
commit 3809ac5470
2 changed files with 5 additions and 1 deletions
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1
artiq/coredevice/phaser.py
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@ -1351,6 +1351,7 @@ class Miqro:
idx = 0 idx = 0
data[word] |= (profiles[i] & 0x1f) << idx data[word] |= (profiles[i] & 0x1f) << idx
idx += 5 idx += 5
delay_mu(-8*word)
while word >= 0: while word >= 0:
rtio_output(self.base_addr + word, data[word]) rtio_output(self.base_addr + word, data[word])
delay_mu(8) delay_mu(8)

5
artiq/gateware/rtio/phy/phaser.py
View File

@ -111,6 +111,9 @@ class MiqroChannel(Module):
If(self.ack, If(self.ack,
dt[1:].eq(0), dt[1:].eq(0),
stb.eq(0), stb.eq(0),
If(stb,
[r.eq(0) for r in regs],
),
), ),
If(self.rtlink.o.stb, If(self.rtlink.o.stb,
Array(regs)[self.rtlink.o.address].eq(self.rtlink.o.data), Array(regs)[self.rtlink.o.address].eq(self.rtlink.o.data),
@ -159,7 +162,7 @@ class Miqro(Module):
re_dly = Signal(3) # stage, send, respond re_dly = Signal(3) # stage, send, respond
self.sync.rtio += [ self.sync.rtio += [
header.type.eq(1), # body type is miqro pulse data header.type.eq(3), # body type is miqro pulse data
If(self.serializer.stb, If(self.serializer.stb,
header.we.eq(0), header.we.eq(0),
re_dly.eq(re_dly[1:]), re_dly.eq(re_dly[1:]),