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https://github.com/m-labs/artiq.git
synced 2024-12-25 03:08:27 +08:00
refactor for 32 bit mem access
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parent
d6d0c2c866
commit
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@ -48,8 +48,8 @@ PHASER_ADDR_SERVO_CFG1 = 0x31
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PHASER_ADDR_SERVO_DATA_BASE = 0x32
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# 0x78 Miqro channel profile/window memories
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PHASER_ADDR_MIQRO_MEM_ADDR = 0x78
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PHASER_ADDR_MIQRO_MEM_DATA = 0x7a
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PHASER_ADDR_MIQRO_MEM_ADDR = 0x72
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PHASER_ADDR_MIQRO_MEM_DATA = 0x74
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PHASER_SEL_DAC = 1 << 0
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PHASER_SEL_TRF0 = 1 << 1
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@ -1285,15 +1285,16 @@ class Miqro:
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self.channel.index) << 8
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@kernel
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def write8(self, addr, data):
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def write32(self, addr, data):
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self.channel.phaser.write16(PHASER_ADDR_MIQRO_MEM_ADDR,
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(self.channel.index << 13) | addr)
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self.channel.phaser.write8(PHASER_ADDR_MIQRO_MEM_DATA, data)
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(self.channel.index << 15) | addr)
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self.channel.phaser.write32(PHASER_ADDR_MIQRO_MEM_DATA, data)
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@kernel
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def write32(self, addr, data):
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for i in range(4):
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self.write8(addr + i, data >> (i * 8))
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def read32(self, addr):
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self.channel.phaser.write16(PHASER_ADDR_MIQRO_MEM_ADDR,
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(self.channel.index << 15) | addr)
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return self.channel.phaser.read32(PHASER_ADDR_MIQRO_MEM_DATA)
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@kernel
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def set_frequency_mu(self, oscillator, profile, ftw):
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@ -1301,7 +1302,7 @@ class Miqro:
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raise ValueError("invalid oscillator index")
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if profile >= 32:
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raise ValueError("invalid profile index")
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self.write32((1 << 12) | (oscillator << 8) | (profile << 3), ftw)
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self.write32((1 << 14) | (oscillator << 6) | (profile << 1), ftw)
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@kernel
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def set_amplitude_phase_mu(self, oscillator, profile, asf, pow=0):
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@ -1309,26 +1310,30 @@ class Miqro:
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raise ValueError("invalid oscillator index")
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if profile >= 32:
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raise ValueError("invalid profile index")
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self.write32((1 << 12) | (oscillator << 8) | (profile << 3) | (1 << 2),
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self.write32((1 << 14) | (oscillator << 6) | (profile << 1) | 1,
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(asf & 0xffff) | (pow << 16))
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@kernel
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def set_window(self, start, data, rate=1, shift=0, order=0, head=1, tail=1):
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def set_window(self, start, data, rate=1, shift=0, order=0, head=0, tail=0):
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if len(data) >= 1 << 10:
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raise ValueError("invalid window length")
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if rate < 1 or rate > 1 << 12:
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raise ValueError("rate out of bounds")
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addr = start << 2
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if shift > 0x3f:
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raise ValueError("shift out of bounds")
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if order > 3:
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raise ValueError("order out of bounds")
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addr = start
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self.write32(addr,
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((start + 1 + len(data)) & 0x3ff)
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| ((rate - 1) << 10)
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| ((shift & 0x3f) << 22)
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| ((order & 3) << 28)
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| (shift << 22)
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| (order << 28)
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| ((head & 1) << 30)
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| ((tail & 1) << 31)
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)
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for i in range(len(data)):
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addr += 4
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addr += 1
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self.write32(addr, (data[i][0] & 0xffff) | (data[i][1] << 16))
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@kernel
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