Expose TTLClockGen for Kasli JSONs (#1886)

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Spaqin 2022-05-06 13:33:42 +08:00 committed by GitHub
parent c440f9fe1b
commit 35f30ddf05
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6 changed files with 15 additions and 9 deletions

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@ -12,6 +12,7 @@ Highlights:
- Kasli-SoC, a new EEM carrier based on a Zynq SoC, enabling much faster kernel execution. - Kasli-SoC, a new EEM carrier based on a Zynq SoC, enabling much faster kernel execution.
- HVAMP_8CH 8 channel HV amplifier for Fastino / Zotinos - HVAMP_8CH 8 channel HV amplifier for Fastino / Zotinos
- Almazny mezzanine board for Mirny - Almazny mezzanine board for Mirny
* TTL device output can be now configured to work as a clock generator.
* Softcore targets now use the RISC-V architecture (VexRiscv) instead of OR1K (mor1kx). * Softcore targets now use the RISC-V architecture (VexRiscv) instead of OR1K (mor1kx).
* Gateware FPU is supported on KC705 and Kasli 2.0. * Gateware FPU is supported on KC705 and Kasli 2.0.
* Faster compilation for large arrays/lists. * Faster compilation for large arrays/lists.

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@ -170,11 +170,11 @@
}, },
"bank_direction_low": { "bank_direction_low": {
"type": "string", "type": "string",
"enum": ["input", "output"] "enum": ["input", "output", "clkgen"]
}, },
"bank_direction_high": { "bank_direction_high": {
"type": "string", "type": "string",
"enum": ["input", "output"] "enum": ["input", "output", "clkgen"]
} }
}, },
"required": ["ports", "bank_direction_low", "bank_direction_high"] "required": ["ports", "bank_direction_low", "bank_direction_high"]

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@ -94,7 +94,8 @@ class PeripheralManager:
def process_dio(self, rtio_offset, peripheral, num_channels=8): def process_dio(self, rtio_offset, peripheral, num_channels=8):
class_names = { class_names = {
"input": "TTLInOut", "input": "TTLInOut",
"output": "TTLOut" "output": "TTLOut",
"clkgen": "TTLClockGen"
} }
classes = [ classes = [
class_names[peripheral["bank_direction_low"]], class_names[peripheral["bank_direction_low"]],

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@ -231,10 +231,8 @@ class Urukul(_EEM):
target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
pads = target.platform.request("urukul{}_dds_reset_sync_in".format(eem)) pads = target.platform.request("urukul{}_dds_reset_sync_in".format(eem))
pad = Signal(reset=0)
target.specials += DifferentialOutput(pad, pads.p, pads.n)
if sync_gen_cls is not None: # AD9910 variant and SYNC_IN from EEM if sync_gen_cls is not None: # AD9910 variant and SYNC_IN from EEM
phy = sync_gen_cls(pad, ftw_width=4) phy = sync_gen_cls(pad=pads.p, pad_n=pads.n, ftw_width=4)
target.submodules += phy target.submodules += phy
target.rtio_channels.append(rtio.Channel.from_phy(phy)) target.rtio_channels.append(rtio.Channel.from_phy(phy))

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@ -5,7 +5,8 @@ from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, edge_counter
def peripheral_dio(module, peripheral, **kwargs): def peripheral_dio(module, peripheral, **kwargs):
ttl_classes = { ttl_classes = {
"input": ttl_serdes_7series.InOut_8X, "input": ttl_serdes_7series.InOut_8X,
"output": ttl_serdes_7series.Output_8X "output": ttl_serdes_7series.Output_8X,
"clkgen": ttl_simple.ClockGen
} }
if len(peripheral["ports"]) != 1: if len(peripheral["ports"]) != 1:
raise ValueError("wrong number of ports") raise ValueError("wrong number of ports")

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@ -145,11 +145,16 @@ class InOut(Module):
class ClockGen(Module): class ClockGen(Module):
def __init__(self, pad, ftw_width=24): def __init__(self, pad, pad_n=None, ftw_width=24, dci=False):
self.rtlink = rtlink.Interface(rtlink.OInterface(ftw_width)) self.rtlink = rtlink.Interface(rtlink.OInterface(ftw_width))
# # # # # #
pad_o = Signal()
if pad_n is None:
self.comb += pad.eq(pad_o)
else:
self.specials += DifferentialOutput(pad_o, pad, pad_n)
ftw = Signal(ftw_width) ftw = Signal(ftw_width)
acc = Signal(ftw_width) acc = Signal(ftw_width)
self.sync.rio += If(self.rtlink.o.stb, ftw.eq(self.rtlink.o.data)) self.sync.rio += If(self.rtlink.o.stb, ftw.eq(self.rtlink.o.data))
@ -165,5 +170,5 @@ class ClockGen(Module):
acc.eq(0) acc.eq(0)
) )
), ),
pad.eq(acc[-1]) pad_o.eq(acc[-1])
] ]