From 35f30ddf054ba123c923efcd3a0ddf28c758ef36 Mon Sep 17 00:00:00 2001 From: Spaqin Date: Fri, 6 May 2022 13:33:42 +0800 Subject: [PATCH] Expose TTLClockGen for Kasli JSONs (#1886) --- RELEASE_NOTES.rst | 1 + artiq/coredevice/coredevice_generic.schema.json | 4 ++-- artiq/frontend/artiq_ddb_template.py | 3 ++- artiq/gateware/eem.py | 4 +--- artiq/gateware/eem_7series.py | 3 ++- artiq/gateware/rtio/phy/ttl_simple.py | 9 +++++++-- 6 files changed, 15 insertions(+), 9 deletions(-) diff --git a/RELEASE_NOTES.rst b/RELEASE_NOTES.rst index 0bd400186..19a97a206 100644 --- a/RELEASE_NOTES.rst +++ b/RELEASE_NOTES.rst @@ -12,6 +12,7 @@ Highlights: - Kasli-SoC, a new EEM carrier based on a Zynq SoC, enabling much faster kernel execution. - HVAMP_8CH 8 channel HV amplifier for Fastino / Zotinos - Almazny mezzanine board for Mirny +* TTL device output can be now configured to work as a clock generator. * Softcore targets now use the RISC-V architecture (VexRiscv) instead of OR1K (mor1kx). * Gateware FPU is supported on KC705 and Kasli 2.0. * Faster compilation for large arrays/lists. diff --git a/artiq/coredevice/coredevice_generic.schema.json b/artiq/coredevice/coredevice_generic.schema.json index 800f0863e..79527cf31 100644 --- a/artiq/coredevice/coredevice_generic.schema.json +++ b/artiq/coredevice/coredevice_generic.schema.json @@ -170,11 +170,11 @@ }, "bank_direction_low": { "type": "string", - "enum": ["input", "output"] + "enum": ["input", "output", "clkgen"] }, "bank_direction_high": { "type": "string", - "enum": ["input", "output"] + "enum": ["input", "output", "clkgen"] } }, "required": ["ports", "bank_direction_low", "bank_direction_high"] diff --git a/artiq/frontend/artiq_ddb_template.py b/artiq/frontend/artiq_ddb_template.py index 4fd3a543f..b6d9294a3 100755 --- a/artiq/frontend/artiq_ddb_template.py +++ b/artiq/frontend/artiq_ddb_template.py @@ -94,7 +94,8 @@ class PeripheralManager: def process_dio(self, rtio_offset, peripheral, num_channels=8): class_names = { "input": "TTLInOut", - "output": "TTLOut" + "output": "TTLOut", + "clkgen": "TTLClockGen" } classes = [ class_names[peripheral["bank_direction_low"]], diff --git a/artiq/gateware/eem.py b/artiq/gateware/eem.py index 6c588b476..23a85eca8 100644 --- a/artiq/gateware/eem.py +++ b/artiq/gateware/eem.py @@ -231,10 +231,8 @@ class Urukul(_EEM): target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) pads = target.platform.request("urukul{}_dds_reset_sync_in".format(eem)) - pad = Signal(reset=0) - target.specials += DifferentialOutput(pad, pads.p, pads.n) if sync_gen_cls is not None: # AD9910 variant and SYNC_IN from EEM - phy = sync_gen_cls(pad, ftw_width=4) + phy = sync_gen_cls(pad=pads.p, pad_n=pads.n, ftw_width=4) target.submodules += phy target.rtio_channels.append(rtio.Channel.from_phy(phy)) diff --git a/artiq/gateware/eem_7series.py b/artiq/gateware/eem_7series.py index 06a2d9b1d..1f5f770c2 100644 --- a/artiq/gateware/eem_7series.py +++ b/artiq/gateware/eem_7series.py @@ -5,7 +5,8 @@ from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, edge_counter def peripheral_dio(module, peripheral, **kwargs): ttl_classes = { "input": ttl_serdes_7series.InOut_8X, - "output": ttl_serdes_7series.Output_8X + "output": ttl_serdes_7series.Output_8X, + "clkgen": ttl_simple.ClockGen } if len(peripheral["ports"]) != 1: raise ValueError("wrong number of ports") diff --git a/artiq/gateware/rtio/phy/ttl_simple.py b/artiq/gateware/rtio/phy/ttl_simple.py index 4484ce3af..192165dc9 100644 --- a/artiq/gateware/rtio/phy/ttl_simple.py +++ b/artiq/gateware/rtio/phy/ttl_simple.py @@ -145,11 +145,16 @@ class InOut(Module): class ClockGen(Module): - def __init__(self, pad, ftw_width=24): + def __init__(self, pad, pad_n=None, ftw_width=24, dci=False): self.rtlink = rtlink.Interface(rtlink.OInterface(ftw_width)) # # # + pad_o = Signal() + if pad_n is None: + self.comb += pad.eq(pad_o) + else: + self.specials += DifferentialOutput(pad_o, pad, pad_n) ftw = Signal(ftw_width) acc = Signal(ftw_width) self.sync.rio += If(self.rtlink.o.stb, ftw.eq(self.rtlink.o.data)) @@ -165,5 +170,5 @@ class ClockGen(Module): acc.eq(0) ) ), - pad.eq(acc[-1]) + pad_o.eq(acc[-1]) ]