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Revert "sawg: advance dds 1/2 by one sample group" 

This reverts commit 8e0a1cbdc8.

c.f. #772

The underlying issue is still the same. You will always find something that does not match when trying to compare the DDS with the parallelized DUC. They are just different. I could correct it for phase but then it will fail for amplitude. Or you'll compare the offset channel to phase1 or amplitude1. Let's state that equal things are well synchronized but unequal things may have a deterministic latency difference of strictly less than one coarse RTIO cycle.
This commit is contained in:
Robert Jördens 2017-07-04 17:54:38 +02:00
parent 8e0a1cbdc8
commit 2f1029c292
1 changed files with 1 additions and 1 deletions
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artiq/gateware/dsp/sawg.py
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@ -163,7 +163,7 @@ class Channel(Module, SatAddMixin):
self.u.latency += 1 # self.o self.u.latency += 1 # self.o
b.p.latency += 1 # self.o b.p.latency += 1 # self.o
b.f.latency += 1 # self.o b.f.latency += 1 # self.o
a_latency_delta = hbf[0].latency + b.latency + 3 # hbf.i, self.o a_latency_delta = hbf[0].latency + b.latency + 2 # hbf.i, self.o
for a in a1, a2: for a in a1, a2:
a.a.latency += a_latency_delta a.a.latency += a_latency_delta
a.p.latency += a_latency_delta a.p.latency += a_latency_delta