From 2f1029c292c8992c13eba703c229310694f4604b Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 4 Jul 2017 17:54:38 +0200 Subject: [PATCH] Revert "sawg: advance dds 1/2 by one sample group" This reverts commit 8e0a1cbdc83db1428f95a252483c5ebc42242b16. c.f. #772 The underlying issue is still the same. You will always find something that does not match when trying to compare the DDS with the parallelized DUC. They are just different. I could correct it for phase but then it will fail for amplitude. Or you'll compare the offset channel to phase1 or amplitude1. Let's state that equal things are well synchronized but unequal things may have a deterministic latency difference of strictly less than one coarse RTIO cycle. --- artiq/gateware/dsp/sawg.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/dsp/sawg.py b/artiq/gateware/dsp/sawg.py index 8bdee6664..2ac997ad2 100644 --- a/artiq/gateware/dsp/sawg.py +++ b/artiq/gateware/dsp/sawg.py @@ -163,7 +163,7 @@ class Channel(Module, SatAddMixin): self.u.latency += 1 # self.o b.p.latency += 1 # self.o b.f.latency += 1 # self.o - a_latency_delta = hbf[0].latency + b.latency + 3 # hbf.i, self.o + a_latency_delta = hbf[0].latency + b.latency + 2 # hbf.i, self.o for a in a1, a2: a.a.latency += a_latency_delta a.p.latency += a_latency_delta