mirror of https://github.com/m-labs/artiq.git
kasli_sawgmaster: generate a HMC830 clock with Urukul
This commit is contained in:
parent
9ae57fd51e
commit
2e8decbce3
|
@ -5,7 +5,20 @@ class SinesUrukulSayma(EnvExperiment):
|
||||||
def build(self):
|
def build(self):
|
||||||
self.setattr_device("core")
|
self.setattr_device("core")
|
||||||
self.setattr_device("urukul0_cpld")
|
self.setattr_device("urukul0_cpld")
|
||||||
self.urukul_chs = [self.get_device("urukul0_ch" + str(i)) for i in range(4)]
|
|
||||||
|
# Urukul clock output syntonized to the RTIO clock.
|
||||||
|
# Can be used as HMC830 reference on Sayma RTM.
|
||||||
|
# The clock output on Sayma AMC cannot be used, as it is derived from
|
||||||
|
# another Si5324 output than the GTH, and the two Si5324 output dividers
|
||||||
|
# are not synchronized with each other.
|
||||||
|
# When using this reference, Sayma must be recalibrated every time Urukul
|
||||||
|
# is rebooted, as Urukul is not synchronized to the Kasli.
|
||||||
|
self.urukul_hmc_ref = self.get_device("urukul0_ch3")
|
||||||
|
|
||||||
|
# Urukul measurement channels - compare with SAWG outputs.
|
||||||
|
# When testing sync, do not reboot Urukul, as it is not
|
||||||
|
# synchronized to the Kasli.
|
||||||
|
self.urukul_meas = [self.get_device("urukul0_ch" + str(i)) for i in range(3)]
|
||||||
self.sawgs = [self.get_device("sawg"+str(i)) for i in range(8)]
|
self.sawgs = [self.get_device("sawg"+str(i)) for i in range(8)]
|
||||||
|
|
||||||
@kernel
|
@kernel
|
||||||
|
@ -18,17 +31,22 @@ class SinesUrukulSayma(EnvExperiment):
|
||||||
@kernel
|
@kernel
|
||||||
def run(self):
|
def run(self):
|
||||||
f = 9*MHz
|
f = 9*MHz
|
||||||
dds_ftw = self.urukul_chs[0].frequency_to_ftw(f)
|
dds_ftw = self.urukul_meas[0].frequency_to_ftw(f)
|
||||||
sawg_ftw = self.sawgs[0].frequency0.to_mu(f)
|
sawg_ftw = self.sawgs[0].frequency0.to_mu(f)
|
||||||
if dds_ftw != sawg_ftw:
|
if dds_ftw != sawg_ftw:
|
||||||
print("DDS and SAWG FTWs do not match:", dds_ftw, sawg_ftw)
|
print("DDS and SAWG FTWs do not match:", dds_ftw, sawg_ftw)
|
||||||
return
|
return
|
||||||
|
|
||||||
# Note: when testing sync, do not reboot Urukul, as it is not
|
|
||||||
# synchronized to the FPGA (yet).
|
|
||||||
self.core.reset()
|
self.core.reset()
|
||||||
self.urukul0_cpld.init()
|
self.urukul0_cpld.init()
|
||||||
for urukul_ch in self.urukul_chs:
|
|
||||||
|
delay(1*ms)
|
||||||
|
self.urukul_hmc_ref.init()
|
||||||
|
self.urukul_hmc_ref.set_mu(0x40000000, asf=self.urukul_hmc_ref.amplitude_to_asf(0.6))
|
||||||
|
self.urukul_hmc_ref.set_att(6.)
|
||||||
|
self.urukul_hmc_ref.sw.on()
|
||||||
|
|
||||||
|
for urukul_ch in self.urukul_meas:
|
||||||
delay(1*ms)
|
delay(1*ms)
|
||||||
urukul_ch.init()
|
urukul_ch.init()
|
||||||
urukul_ch.set_mu(dds_ftw, asf=urukul_ch.amplitude_to_asf(0.5))
|
urukul_ch.set_mu(dds_ftw, asf=urukul_ch.amplitude_to_asf(0.5))
|
||||||
|
|
Loading…
Reference in New Issue