From 2d4a1340ea3a25dbaaa2200b7e86d2f42e7a19b5 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 7 Feb 2018 12:27:35 +0800 Subject: [PATCH] sayma_amc: remove RTM bitstream upload core. Closes #908 --- artiq/gateware/targets/sayma_amc.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index c45f8d37a..b25a924cb 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -160,9 +160,10 @@ class Standalone(MiniSoC, AMPSoC): ] # RTM bitstream upload - rtm_fpga_cfg = platform.request("rtm_fpga_cfg") - self.submodules.rtm_fpga_cfg = SlaveFPGA(rtm_fpga_cfg) - self.csr_devices.append("rtm_fpga_cfg") + # https://github.com/m-labs/artiq/issues/908#issuecomment-363650534 + #rtm_fpga_cfg = platform.request("rtm_fpga_cfg") + #self.submodules.rtm_fpga_cfg = SlaveFPGA(rtm_fpga_cfg) + #self.csr_devices.append("rtm_fpga_cfg") # AMC/RTM serwb serwb_pll = serwb.phy.SERWBPLL(125e6, 625e6, vco_div=2)