mirror of https://github.com/m-labs/artiq.git
278 lines
10 KiB
Python
Executable File
278 lines
10 KiB
Python
Executable File
#!/usr/bin/env python3
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import argparse
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import json
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from misoc.integration.builder import builder_args, builder_argdict
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from misoc.targets.kasli import soc_kasli_args, soc_kasli_argdict
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, edge_counter
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from artiq.gateware import eem
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from artiq.gateware.targets.kasli import StandaloneBase, MasterBase, SatelliteBase
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from artiq.build_soc import *
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def peripheral_dio(module, peripheral):
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ttl_classes = {
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"input": ttl_serdes_7series.InOut_8X,
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"output": ttl_serdes_7series.Output_8X
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}
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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if peripheral.get("edge_counter", False):
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edge_counter_cls = edge_counter.SimpleEdgeCounter
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else:
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edge_counter_cls = None
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eem.DIO.add_std(module, peripheral["ports"][0],
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ttl_classes[peripheral["bank_direction_low"]],
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ttl_classes[peripheral["bank_direction_high"]],
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edge_counter_cls=edge_counter_cls)
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def peripheral_urukul(module, peripheral):
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if len(peripheral["ports"]) == 1:
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port, port_aux = peripheral["ports"][0], None
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elif len(peripheral["ports"]) == 2:
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port, port_aux = peripheral["ports"]
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else:
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raise ValueError("wrong number of ports")
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if peripheral.get("synchronization", False):
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sync_gen_cls = ttl_simple.ClockGen
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else:
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sync_gen_cls = None
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eem.Urukul.add_std(module, port, port_aux, ttl_serdes_7series.Output_8X,
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sync_gen_cls)
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def peripheral_novogorny(module, peripheral):
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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eem.Novogorny.add_std(module, peripheral["ports"][0], ttl_serdes_7series.Output_8X)
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def peripheral_sampler(module, peripheral):
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if len(peripheral["ports"]) == 1:
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port, port_aux = peripheral["ports"][0], None
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elif len(peripheral["ports"]) == 2:
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port, port_aux = peripheral["ports"]
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else:
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raise ValueError("wrong number of ports")
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eem.Sampler.add_std(module, port, port_aux, ttl_serdes_7series.Output_8X)
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def peripheral_suservo(module, peripheral):
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if len(peripheral["sampler_ports"]) != 2:
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raise ValueError("wrong number of Sampler ports")
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urukul_ports = []
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if len(peripheral["urukul0_ports"]) != 2:
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raise ValueError("wrong number of Urukul #0 ports")
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urukul_ports.append(peripheral["urukul0_ports"])
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if "urukul1_ports" in peripheral:
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if len(peripheral["urukul1_ports"]) != 2:
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raise ValueError("wrong number of Urukul #1 ports")
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urukul_ports.append(peripheral["urukul1_ports"])
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eem.SUServo.add_std(module,
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peripheral["sampler_ports"],
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urukul_ports)
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def peripheral_zotino(module, peripheral):
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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eem.Zotino.add_std(module, peripheral["ports"][0],
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ttl_serdes_7series.Output_8X)
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def peripheral_grabber(module, peripheral):
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if len(peripheral["ports"]) == 1:
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port = peripheral["ports"][0]
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port_aux = None
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port_aux2 = None
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elif len(peripheral["ports"]) == 2:
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port, port_aux = peripheral["ports"]
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port_aux2 = None
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elif len(peripheral["ports"]) == 3:
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port, port_aux, port_aux2 = peripheral["ports"]
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else:
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raise ValueError("wrong number of ports")
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eem.Grabber.add_std(module, port, port_aux, port_aux2)
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def peripheral_mirny(module, peripheral):
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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eem.Mirny.add_std(module, peripheral["ports"][0],
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ttl_serdes_7series.Output_8X)
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def peripheral_fastino(module, peripheral):
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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eem.Fastino.add_std(module, peripheral["ports"][0])
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peripheral_processors = {
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"dio": peripheral_dio,
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"urukul": peripheral_urukul,
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"novogorny": peripheral_novogorny,
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"sampler": peripheral_sampler,
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"suservo": peripheral_suservo,
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"zotino": peripheral_zotino,
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"grabber": peripheral_grabber,
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"mirny": peripheral_mirny,
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"fastino": peripheral_fastino,
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}
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def add_peripherals(module, peripherals):
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for peripheral in peripherals:
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peripheral_processors[peripheral["type"]](module, peripheral)
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class GenericStandalone(StandaloneBase):
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def __init__(self, description, hw_rev=None,**kwargs):
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if hw_rev is None:
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hw_rev = description["hw_rev"]
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self.class_name_override = description["variant"]
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StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = "{:.1f}".format(description.get("rtio_frequency", 125e6)/1e6)
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if "ext_ref_frequency" in description:
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self.config["SI5324_EXT_REF"] = None
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self.config["EXT_REF_FREQUENCY"] = "{:.1f}".format(
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description["ext_ref_frequency"]/1e6)
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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self.grabber_csr_group = []
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self.rtio_channels = []
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add_peripherals(self, description["peripherals"])
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for i in (1, 2):
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print("SFP LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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sfp_ctl = self.platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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if has_grabber:
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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for grabber in self.grabber_csr_group:
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self.platform.add_false_path_constraints(
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self.rtio_crg.cd_rtio.clk, getattr(self, grabber).deserializer.cd_cl.clk)
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class GenericMaster(MasterBase):
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def __init__(self, description, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = description["hw_rev"]
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self.class_name_override = description["variant"]
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MasterBase.__init__(self,
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hw_rev=hw_rev,
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rtio_clk_freq=description.get("rtio_frequency", 125e6),
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enable_sata=description.get("enable_sata_drtio", False),
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**kwargs)
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if "ext_ref_frequency" in description:
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self.config["SI5324_EXT_REF"] = None
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self.config["EXT_REF_FREQUENCY"] = "{:.1f}".format(
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description["ext_ref_frequency"]/1e6)
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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self.grabber_csr_group = []
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self.rtio_channels = []
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add_peripherals(self, description["peripherals"])
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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if has_grabber:
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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for grabber in self.grabber_csr_group:
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self.platform.add_false_path_constraints(
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self.drtio_transceiver.gtps[0].txoutclk, getattr(self, grabber).deserializer.cd_cl.clk)
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class GenericSatellite(SatelliteBase):
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def __init__(self, description, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = description["hw_rev"]
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self.class_name_override = description["variant"]
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SatelliteBase.__init__(self,
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hw_rev=hw_rev,
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rtio_clk_freq=description.get("rtio_frequency", 125e6),
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enable_sata=description.get("enable_sata_drtio", False),
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**kwargs)
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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self.grabber_csr_group = []
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self.rtio_channels = []
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add_peripherals(self, description["peripherals"])
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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if has_grabber:
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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for grabber in self.grabber_csr_group:
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self.platform.add_false_path_constraints(
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self.drtio_transceiver.gtps[0].txoutclk, getattr(self, grabber).deserializer.cd_cl.clk)
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder for generic Kasli systems")
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builder_args(parser)
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soc_kasli_args(parser)
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parser.set_defaults(output_dir="artiq_kasli")
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parser.add_argument("description", metavar="DESCRIPTION",
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help="JSON system description file")
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args = parser.parse_args()
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with open(args.description, "r") as f:
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description = json.load(f)
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if description["target"] != "kasli":
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raise ValueError("Description is for a different target")
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if description["base"] == "standalone":
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cls = GenericStandalone
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elif description["base"] == "master":
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cls = GenericMaster
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elif description["base"] == "satellite":
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cls = GenericSatellite
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else:
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raise ValueError("Invalid base")
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soc = cls(description, **soc_kasli_argdict(args))
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args.variant = description["variant"]
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build_artiq_soc(soc, builder_argdict(args))
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if __name__ == "__main__":
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main()
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