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targets: configure L2 line size (#2647)

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occheung 2025-01-16 13:05:39 +08:00 committed by GitHub
parent 8ce6048c96
commit 2b48822fe3
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3 changed files with 7 additions and 0 deletions
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1
artiq/gateware/targets/efc.py
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@ -36,6 +36,7 @@ class Satellite(BaseSoC, AMPSoC):
cpu_bus_width=64,
sdram_controller_type="minicon",
l2_size=128*1024,
l2_line_size=64,
clk_freq=125e6,
**kwargs)
AMPSoC.__init__(self)

3
artiq/gateware/targets/kasli.py
View File

@ -68,6 +68,7 @@ class StandaloneBase(MiniSoC, AMPSoC):
cpu_bus_width=cpu_bus_width,
sdram_controller_type="minicon",
l2_size=128*1024,
l2_line_size=64,
integrated_sram_size=8192,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
@ -176,6 +177,7 @@ class MasterBase(MiniSoC, AMPSoC):
cpu_bus_width=cpu_bus_width,
sdram_controller_type="minicon",
l2_size=128*1024,
l2_line_size=64,
integrated_sram_size=8192,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
@ -427,6 +429,7 @@ class SatelliteBase(BaseSoC, AMPSoC):
cpu_bus_width=cpu_bus_width,
sdram_controller_type="minicon",
l2_size=128*1024,
l2_line_size=64,
clk_freq=rtio_clk_freq,
rtio_sys_merge=True,
**kwargs)

3
artiq/gateware/targets/kc705.py
View File

@ -90,6 +90,7 @@ class _StandaloneBase(MiniSoC, AMPSoC):
cpu_bus_width=64,
sdram_controller_type="minicon",
l2_size=128*1024,
l2_line_size=64,
integrated_sram_size=8192,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
@ -187,6 +188,7 @@ class _MasterBase(MiniSoC, AMPSoC):
cpu_bus_width=64,
sdram_controller_type="minicon",
l2_size=128*1024,
l2_line_size=64,
integrated_sram_size=8192,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
@ -335,6 +337,7 @@ class _SatelliteBase(BaseSoC, AMPSoC):
cpu_bus_width=64,
sdram_controller_type="minicon",
l2_size=128*1024,
l2_line_size=64,
integrated_sram_size=8192,
clk_freq=clk_freq,
rtio_sys_merge=True,