From 2b48822fe37f4aef6703de57dad449cfef1422ce Mon Sep 17 00:00:00 2001
From: occheung <54844539+occheung@users.noreply.github.com>
Date: Thu, 16 Jan 2025 13:05:39 +0800
Subject: [PATCH] targets: configure L2 line size (#2647)

---
 artiq/gateware/targets/efc.py   | 1 +
 artiq/gateware/targets/kasli.py | 3 +++
 artiq/gateware/targets/kc705.py | 3 +++
 3 files changed, 7 insertions(+)

diff --git a/artiq/gateware/targets/efc.py b/artiq/gateware/targets/efc.py
index 385e05479..81c77b5be 100644
--- a/artiq/gateware/targets/efc.py
+++ b/artiq/gateware/targets/efc.py
@@ -36,6 +36,7 @@ class Satellite(BaseSoC, AMPSoC):
                  cpu_bus_width=64,
                  sdram_controller_type="minicon",
                  l2_size=128*1024,
+                 l2_line_size=64,
                  clk_freq=125e6,
                  **kwargs)
         AMPSoC.__init__(self)
diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py
index af3db6a68..0e912c581 100755
--- a/artiq/gateware/targets/kasli.py
+++ b/artiq/gateware/targets/kasli.py
@@ -68,6 +68,7 @@ class StandaloneBase(MiniSoC, AMPSoC):
                          cpu_bus_width=cpu_bus_width,
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
+                         l2_line_size=64,
                          integrated_sram_size=8192,
                          ethmac_nrxslots=4,
                          ethmac_ntxslots=4,
@@ -176,6 +177,7 @@ class MasterBase(MiniSoC, AMPSoC):
                          cpu_bus_width=cpu_bus_width,
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
+                         l2_line_size=64,
                          integrated_sram_size=8192,
                          ethmac_nrxslots=4,
                          ethmac_ntxslots=4,
@@ -427,6 +429,7 @@ class SatelliteBase(BaseSoC, AMPSoC):
                  cpu_bus_width=cpu_bus_width,
                  sdram_controller_type="minicon",
                  l2_size=128*1024,
+                 l2_line_size=64,
                  clk_freq=rtio_clk_freq,
                  rtio_sys_merge=True,
                  **kwargs)
diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
index f7b951872..623621179 100755
--- a/artiq/gateware/targets/kc705.py
+++ b/artiq/gateware/targets/kc705.py
@@ -90,6 +90,7 @@ class _StandaloneBase(MiniSoC, AMPSoC):
                          cpu_bus_width=64,
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
+                         l2_line_size=64,
                          integrated_sram_size=8192,
                          ethmac_nrxslots=4,
                          ethmac_ntxslots=4,
@@ -187,6 +188,7 @@ class _MasterBase(MiniSoC, AMPSoC):
                          cpu_bus_width=64,
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
+                         l2_line_size=64,
                          integrated_sram_size=8192,
                          ethmac_nrxslots=4,
                          ethmac_ntxslots=4,
@@ -335,6 +337,7 @@ class _SatelliteBase(BaseSoC, AMPSoC):
                  cpu_bus_width=64,
                  sdram_controller_type="minicon",
                  l2_size=128*1024,
+                 l2_line_size=64,
                  integrated_sram_size=8192,
                  clk_freq=clk_freq,
                  rtio_sys_merge=True,