M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

suservo: remove adc return clock gating

This commit is contained in:
Robert Jördens 2018-05-12 22:10:40 +00:00
parent 74c0b4452b
commit 2a47b934ea
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
artiq/gateware/suservo/adc_ser.py
View File

@ -107,7 +107,7 @@ class ADC(Module):
) )
try: try:
sck_en_ret = pads.sck_en_ret sck_en_ret = pads.sck_en_ret # simulation
except AttributeError: except AttributeError:
sck_en_ret = 1 sck_en_ret = 1
@ -119,7 +119,7 @@ class ADC(Module):
for i, sdo in enumerate(sdo): for i, sdo in enumerate(sdo):
sdo_sr = Signal(2*t_read) sdo_sr = Signal(2*t_read)
self.sync.ret += [ self.sync.ret += [
If(self.reading & sck_en_ret, If(sck_en_ret,
sdo_sr[1:].eq(sdo_sr), sdo_sr[1:].eq(sdo_sr),
sdo_sr[0].eq(sdo), sdo_sr[0].eq(sdo),
) )