From 2a47b934eafd8654c18751fce074bd33cd4b17e3 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Sat, 12 May 2018 22:10:40 +0000 Subject: [PATCH] suservo: remove adc return clock gating --- artiq/gateware/suservo/adc_ser.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/suservo/adc_ser.py b/artiq/gateware/suservo/adc_ser.py index 93d471fcb..9e2bf48b9 100644 --- a/artiq/gateware/suservo/adc_ser.py +++ b/artiq/gateware/suservo/adc_ser.py @@ -107,7 +107,7 @@ class ADC(Module): ) try: - sck_en_ret = pads.sck_en_ret + sck_en_ret = pads.sck_en_ret # simulation except AttributeError: sck_en_ret = 1 @@ -119,7 +119,7 @@ class ADC(Module): for i, sdo in enumerate(sdo): sdo_sr = Signal(2*t_read) self.sync.ret += [ - If(self.reading & sck_en_ret, + If(sck_en_ret, sdo_sr[1:].eq(sdo_sr), sdo_sr[0].eq(sdo), )