mirror of https://github.com/m-labs/artiq.git
remove use of _r prefix on CSRs
This commit is contained in:
Florent Kermarrec
parent
88a1707ef9
commit
2995f0a705
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@ -308,32 +308,32 @@ class RTIO(Module, AutoCSR):
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phy.rbus, self.counter, fine_ts_width, ififo_depth)
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# CSRs
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self._r_reset = CSRStorage(reset=1)
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self._r_chan_sel = CSRStorage(flen(self.bank_o.sel))
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self._reset = CSRStorage(reset=1)
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self._chan_sel = CSRStorage(flen(self.bank_o.sel))
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self._r_oe = CSR()
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self._oe = CSR()
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self._r_o_timestamp = CSRStorage(counter_width + fine_ts_width)
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self._r_o_value = CSRStorage(2)
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self._r_o_we = CSR()
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self._r_o_status = CSRStatus(3)
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self._r_o_underflow_reset = CSR()
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self._r_o_sequence_error_reset = CSR()
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self._o_timestamp = CSRStorage(counter_width + fine_ts_width)
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self._o_value = CSRStorage(2)
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self._o_we = CSR()
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self._o_status = CSRStatus(3)
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self._o_underflow_reset = CSR()
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self._o_sequence_error_reset = CSR()
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self._r_i_timestamp = CSRStatus(counter_width + fine_ts_width)
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self._r_i_value = CSRStatus()
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self._r_i_re = CSR()
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self._r_i_status = CSRStatus(2)
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self._r_i_overflow_reset = CSR()
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self._r_i_pileup_count = CSRStatus(16)
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self._r_i_pileup_reset = CSR()
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self._i_timestamp = CSRStatus(counter_width + fine_ts_width)
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self._i_value = CSRStatus()
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self._i_re = CSR()
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self._i_status = CSRStatus(2)
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self._i_overflow_reset = CSR()
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self._i_pileup_count = CSRStatus(16)
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self._i_pileup_reset = CSR()
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self._r_counter = CSRStatus(counter_width + fine_ts_width)
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self._r_counter_update = CSR()
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self._counter = CSRStatus(counter_width + fine_ts_width)
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self._counter_update = CSR()
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self._r_frequency_i = CSRStatus(32)
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self._r_frequency_fn = CSRStatus(8)
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self._r_frequency_fd = CSRStatus(8)
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self._frequency_i = CSRStatus(32)
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self._frequency_fn = CSRStatus(8)
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self._frequency_fd = CSRStatus(8)
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# Clocking/Reset
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@ -343,54 +343,54 @@ class RTIO(Module, AutoCSR):
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self.clock_domains.cd_rio = ClockDomain()
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self.comb += [
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self.cd_rsys.clk.eq(ClockSignal()),
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self.cd_rsys.rst.eq(self._r_reset.storage)
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self.cd_rsys.rst.eq(self._reset.storage)
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]
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self.comb += self.cd_rio.clk.eq(ClockSignal("rtio"))
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self.specials += AsyncResetSynchronizer(
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self.cd_rio, self._r_reset.storage)
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self.cd_rio, self._reset.storage)
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# OE
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oes = []
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for n, chif in enumerate(phy.rbus):
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if hasattr(chif, "oe"):
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self.sync += \
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If(self._r_oe.re & (self._r_chan_sel.storage == n),
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chif.oe.eq(self._r_oe.r)
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If(self._oe.re & (self._chan_sel.storage == n),
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chif.oe.eq(self._oe.r)
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)
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oes.append(chif.oe)
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else:
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oes.append(1)
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self.comb += self._r_oe.w.eq(Array(oes)[self._r_chan_sel.storage])
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self.comb += self._oe.w.eq(Array(oes)[self._chan_sel.storage])
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# Output/Gate
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self.comb += [
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self.bank_o.sel.eq(self._r_chan_sel.storage),
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self.bank_o.timestamp.eq(self._r_o_timestamp.storage),
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self.bank_o.value.eq(self._r_o_value.storage),
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self.bank_o.we.eq(self._r_o_we.re),
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self._r_o_status.status.eq(Cat(~self.bank_o.writable,
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self.bank_o.sel.eq(self._chan_sel.storage),
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self.bank_o.timestamp.eq(self._o_timestamp.storage),
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self.bank_o.value.eq(self._o_value.storage),
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self.bank_o.we.eq(self._o_we.re),
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self._o_status.status.eq(Cat(~self.bank_o.writable,
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self.bank_o.underflow,
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self.bank_o.sequence_error)),
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self.bank_o.underflow_reset.eq(self._r_o_underflow_reset.re),
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self.bank_o.sequence_error_reset.eq(self._r_o_sequence_error_reset.re)
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self.bank_o.underflow_reset.eq(self._o_underflow_reset.re),
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self.bank_o.sequence_error_reset.eq(self._o_sequence_error_reset.re)
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]
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# Input
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self.comb += [
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self.bank_i.sel.eq(self._r_chan_sel.storage),
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self._r_i_timestamp.status.eq(self.bank_i.timestamp),
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self._r_i_value.status.eq(self.bank_i.value),
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self.bank_i.re.eq(self._r_i_re.re),
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self._r_i_status.status.eq(Cat(~self.bank_i.readable, self.bank_i.overflow)),
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self.bank_i.overflow_reset.eq(self._r_i_overflow_reset.re),
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self._r_i_pileup_count.status.eq(self.bank_i.pileup_count),
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self.bank_i.pileup_reset.eq(self._r_i_pileup_reset.re)
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self.bank_i.sel.eq(self._chan_sel.storage),
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self._i_timestamp.status.eq(self.bank_i.timestamp),
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self._i_value.status.eq(self.bank_i.value),
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self.bank_i.re.eq(self._i_re.re),
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self._i_status.status.eq(Cat(~self.bank_i.readable, self.bank_i.overflow)),
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self.bank_i.overflow_reset.eq(self._i_overflow_reset.re),
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self._i_pileup_count.status.eq(self.bank_i.pileup_count),
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self.bank_i.pileup_reset.eq(self._i_pileup_reset.re)
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]
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# Counter access
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self.sync += \
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If(self._r_counter_update.re,
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self._r_counter.status.eq(Cat(Replicate(0, fine_ts_width),
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If(self._counter_update.re,
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self._counter.status.eq(Cat(Replicate(0, fine_ts_width),
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self.counter.o_value_sys))
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)
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@ -399,7 +399,7 @@ class RTIO(Module, AutoCSR):
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clk_freq_i = int(clk_freq)
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clk_freq_f = clk_freq - clk_freq_i
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self.comb += [
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self._r_frequency_i.status.eq(clk_freq_i),
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self._r_frequency_fn.status.eq(clk_freq_f.numerator),
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self._r_frequency_fd.status.eq(clk_freq_f.denominator)
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self._frequency_i.status.eq(clk_freq_i),
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self._frequency_fn.status.eq(clk_freq_f.numerator),
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self._frequency_fd.status.eq(clk_freq_f.denominator)
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]
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@ -52,7 +52,7 @@ _tester_io = [
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class _RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, rtio_internal_clk):
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self._r_clock_sel = CSRStorage()
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self._clock_sel = CSRStorage()
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self.clock_domains.cd_rtio = ClockDomain()
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rtio_external_clk = Signal()
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@ -64,7 +64,7 @@ class _RTIOCRG(Module, AutoCSR):
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self.specials += Instance("BUFGMUX",
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i_I0=rtio_internal_clk,
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i_I1=rtio_external_clk,
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i_S=self._r_clock_sel.storage,
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i_S=self._clock_sel.storage,
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o_O=self.cd_rtio.clk)
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@ -52,7 +52,7 @@ _tester_io = [
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class _RTIOMiniCRG(Module, AutoCSR):
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def __init__(self, platform):
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self._r_clock_sel = CSRStorage()
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self._clock_sel = CSRStorage()
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self.clock_domains.cd_rtio = ClockDomain()
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# 80MHz -> 125MHz
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@ -75,7 +75,7 @@ class _RTIOMiniCRG(Module, AutoCSR):
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self.specials += Instance("BUFGMUX",
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i_I0=rtio_internal_clk,
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i_I1=rtio_external_clk,
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i_S=self._r_clock_sel.storage,
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i_S=self._clock_sel.storage,
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o_O=self.cd_rtio.clk)
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platform.add_platform_command("""
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@ -56,7 +56,7 @@ class _TestGen(Module):
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class _RTIOMiniCRG(Module, AutoCSR):
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def __init__(self, platform):
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self._r_clock_sel = CSRStorage()
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self._clock_sel = CSRStorage()
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self.clock_domains.cd_rtio = ClockDomain()
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# 80MHz -> 125MHz
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@ -75,7 +75,7 @@ class _RTIOMiniCRG(Module, AutoCSR):
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self.specials += Instance("BUFGMUX",
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i_I0=rtio_internal_clk,
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i_I1=rtio_external_clk,
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i_S=self._r_clock_sel.storage,
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i_S=self._clock_sel.storage,
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o_O=self.cd_rtio.clk)
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platform.add_platform_command("""
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