mirror of https://github.com/m-labs/artiq.git
rtio: when rtlink addresses are different, issue collision not replace (fixes #320)
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@ -130,19 +130,23 @@ class _OutputManager(Module):
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any_error = Signal()
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nop = Signal()
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self.sync.rsys += [
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# Note: replace does not perform any RTLink address checks,
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# i.e. a write to a different address will be silently replaced
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# as well.
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# Note: replace may be asserted at the same time as collision
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# when addresses are different. In that case, it is a collision.
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replace.eq(self.ev.timestamp == buf.timestamp),
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# Detect sequence errors on coarse timestamps only
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# so that they are mutually exclusive with collision errors.
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sequence_error.eq(self.ev.timestamp[fine_ts_width:]
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< buf.timestamp[fine_ts_width:])
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]
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if hasattr(self.ev, "a"):
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different_addresses = self.ev.a != buf.a
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else:
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different_addresses = 0
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if fine_ts_width:
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self.sync.rsys += collision.eq(
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(self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
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& (self.ev.timestamp[:fine_ts_width] != buf.timestamp[:fine_ts_width]))
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& ((self.ev.timestamp[:fine_ts_width] != buf.timestamp[:fine_ts_width])
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|different_addresses))
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self.comb += any_error.eq(sequence_error | collision)
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if interface.suppress_nop:
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# disable NOP at reset: do not suppress a first write with all 0s
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@ -163,6 +163,17 @@ class Collision(EnvExperiment):
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delay_mu(1)
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class AddressCollision(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("loop_in")
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@kernel
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def run(self):
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self.loop_in.input()
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self.loop_in.pulse(10*us)
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class TimeKeepsRunning(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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@ -224,6 +235,10 @@ class CoredeviceTest(ExperimentCase):
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with self.assertRaises(RTIOCollision):
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self.execute(Collision)
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def test_address_collision(self):
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with self.assertRaises(RTIOCollision):
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self.execute(AddressCollision)
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def test_watchdog(self):
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# watchdog only works on the device
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with self.assertRaises(IOError):
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