drtio: add rt_controller_repeater

This commit is contained in:
Sebastien Bourdeauducq 2018-09-05 16:08:40 +08:00
parent 839f748a1d
commit 2884d595b3
3 changed files with 50 additions and 5 deletions

View File

@ -10,7 +10,8 @@ from artiq.gateware.rtio.sed.core import *
from artiq.gateware.rtio.input_collector import *
from artiq.gateware.drtio import (link_layer, aux_controller,
rt_packet_satellite, rt_errors_satellite,
rt_packet_master, rt_controller_master)
rt_packet_master, rt_controller_master,
rt_controller_repeater)
from artiq.gateware.drtio.rx_synchronizer import GenericRXSynchronizer
@ -188,6 +189,7 @@ class DRTIORepeater(Module):
self.submodules.link_stats = link_layer.LinkLayerStats(self.link_layer, "rtio_rx")
self.submodules.rt_packet = rt_packet_repeater.RTPacketRepeater(tsc, self.link_layer)
self.submodules.rt_controller = rt_controller_repeater.RTController(self.rt_packet)
self.submodules.aux_controller = aux_controller.AuxController(
self.link_layer)
@ -195,6 +197,7 @@ class DRTIORepeater(Module):
def get_csrs(self):
return (self.link_layer.get_csrs() +
self.link_stats.get_csrs() +
self.rt_controller.get_csrs() +
self.aux_controller.get_csrs())
@property

View File

@ -0,0 +1,42 @@
from migen import *
from misoc.interconnect.csr import *
from artiq.gateware.rtio.cdc import BlindTransfer
class RTController(Module, AutoCSR):
def __init__(self, rt_packet):
self.set_time = CSR()
self.protocol_error = CSR(4)
set_time_stb = Signal()
set_time_ack = Signal()
self.submodules += CrossDomainRequest("rtio",
set_time_stb, set_time_ack, None,
rt_packet.set_time_stb, rt_packet.set_time_ack, None)
self.sync += [
If(set_time_ack, set_time_stb.eq(0)),
If(self.set_time.re, set_time_stb.eq(1))
]
self.comb += self.set_time.w.eq(set_time_stb)
errors = [
(rt_packet.err_unknown_packet_type, "rtio_rx"),
(rt_packet.err_packet_truncated, "rtio_rx"),
(rt_packet.err_command_missed, "rtio"),
(rt_packet.err_buffer_space_timeout, "rtio")
]
for n, (err_i, err_cd) in enumerate(errors):
xfer = BlindTransfer(err_cd, "sys")
self.submodules += xfer
self.comb += xfer.i.eq(err_i)
err_pending = Signal()
self.sync += [
If(self.protocol_error.re & self.protocol_error.r[n], err_pending.eq(0)),
If(xfer.o, err_pending.eq(1))
]
self.comb += self.protocol_error.w[n].eq(err_pending)

View File

@ -18,8 +18,8 @@ class RTPacketRepeater(Module):
self.err_packet_truncated = Signal()
# in rtio domain
self.command_missed = Signal()
self.buffer_space_timeout = Signal()
self.err_command_missed = Signal()
self.err_buffer_space_timeout = Signal()
# set_time interface, in rtio domain
self.set_time_stb = Signal()
@ -103,7 +103,7 @@ class RTPacketRepeater(Module):
# Missed commands
cri_ready = Signal()
self.sync.rtio += self.command_missed.eq(~cri_ready & (self.cri.cmd != cri.commands["nop"]))
self.sync.rtio += self.err_command_missed.eq(~cri_ready & (self.cri.cmd != cri.commands["nop"]))
# TX FSM
tx_fsm = ClockDomainsRenamer("rtio")(FSM(reset_state="IDLE"))
@ -158,7 +158,7 @@ class RTPacketRepeater(Module):
tx_fsm.act("WAIT_BUFFER_SPACE",
timeout_counter.wait.eq(1),
If(timeout_counter.done,
self.buffer_space_timeout.eq(1),
self.err_buffer_space_timeout.eq(1),
NextState("IDLE")
).Else(
If(buffer_space_not,