mirror of https://github.com/m-labs/artiq.git
43 lines
1.4 KiB
Python
43 lines
1.4 KiB
Python
from migen import *
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from misoc.interconnect.csr import *
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from artiq.gateware.rtio.cdc import BlindTransfer
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class RTController(Module, AutoCSR):
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def __init__(self, rt_packet):
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self.set_time = CSR()
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self.protocol_error = CSR(4)
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set_time_stb = Signal()
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set_time_ack = Signal()
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self.submodules += CrossDomainRequest("rtio",
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set_time_stb, set_time_ack, None,
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rt_packet.set_time_stb, rt_packet.set_time_ack, None)
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self.sync += [
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If(set_time_ack, set_time_stb.eq(0)),
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If(self.set_time.re, set_time_stb.eq(1))
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]
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self.comb += self.set_time.w.eq(set_time_stb)
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errors = [
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(rt_packet.err_unknown_packet_type, "rtio_rx"),
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(rt_packet.err_packet_truncated, "rtio_rx"),
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(rt_packet.err_command_missed, "rtio"),
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(rt_packet.err_buffer_space_timeout, "rtio")
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]
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for n, (err_i, err_cd) in enumerate(errors):
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xfer = BlindTransfer(err_cd, "sys")
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self.submodules += xfer
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self.comb += xfer.i.eq(err_i)
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err_pending = Signal()
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self.sync += [
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If(self.protocol_error.re & self.protocol_error.r[n], err_pending.eq(0)),
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If(xfer.o, err_pending.eq(1))
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]
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self.comb += self.protocol_error.w[n].eq(err_pending)
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