sdram: reject read delay wrap arounds

artiq/firmware/libboard/sdram.rs

@@ -321,6 +321,8 @@ mod ddr {
             let mut min_delay = 0;
             let mut have_min_delay = false;
             let mut max_delay = 0;
+            let mut have_max_delay = false;
+            let mut have_invalid = 0;
 
             ddrphy::rdly_dq_rst_write(1);
 
@@ -347,8 +349,15 @@ mod ddr {
                         min_delay = delay;
                         have_min_delay = true;
                     }
+                    if !have_max_delay {
                         max_delay = delay;
                     }
+                } else if have_min_delay {
+                    have_invalid += 1;
+                    if have_invalid >= 10 {
+                        have_max_delay = true;
+                    }
+                }
                 ddrphy::rdly_dq_inc_write(1);
             }