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https://github.com/m-labs/artiq.git
synced 2024-12-29 13:13:34 +08:00
firmware: move clock to libboard
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bb056c1d2c
commit
26e7f68b5d
artiq/firmware
@ -1,4 +1,5 @@
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use csr;
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use clock;
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mod ad9154_reg;
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fn spi_setup() {
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@ -133,13 +134,13 @@ fn dac_setup() -> Result<(), &'static str> {
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0*ad9154_reg::LSBFIRST_M | 0*ad9154_reg::LSBFIRST |
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0*ad9154_reg::ADDRINC_M | 0*ad9154_reg::ADDRINC |
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1*ad9154_reg::SDOACTIVE_M | 1*ad9154_reg::SDOACTIVE);
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busywait_us(100);
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clock::spin_us(100);
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write(ad9154_reg::SPI_INTFCONFA,
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0*ad9154_reg::SOFTRESET_M | 0*ad9154_reg::SOFTRESET |
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0*ad9154_reg::LSBFIRST_M | 0*ad9154_reg::LSBFIRST |
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0*ad9154_reg::ADDRINC_M | 0*ad9154_reg::ADDRINC |
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1*ad9154_reg::SDOACTIVE_M | 1*ad9154_reg::SDOACTIVE);
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busywait_us(100);
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clock::spin_us(100);
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if read(ad9154_reg::PRODIDH) as u16 << 8 |
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read(ad9154_reg::PRODIDL) as u16 != 0x9154 {
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return Err("AD9154 not found")
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@ -149,7 +150,7 @@ fn dac_setup() -> Result<(), &'static str> {
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0*ad9154_reg::PD_DAC0 | 0*ad9154_reg::PD_DAC1 |
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0*ad9154_reg::PD_DAC2 | 0*ad9154_reg::PD_DAC3 |
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0*ad9154_reg::PD_BG);
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busywait_us(100);
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clock::spin_us(100);
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write(ad9154_reg::TXENMASK1, 0*ad9154_reg::DACA_MASK |
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0*ad9154_reg::DACB_MASK); // TX not controlled by TXEN pins
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write(ad9154_reg::CLKCFG0,
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@ -348,7 +349,7 @@ fn dac_setup() -> Result<(), &'static str> {
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0x9*ad9154_reg::SYNCMODE | 1*ad9154_reg::SYNCENABLE |
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1*ad9154_reg::SYNCARM | 0*ad9154_reg::SYNCCLRSTKY |
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0*ad9154_reg::SYNCCLRLAST);
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busywait_us(1000); // ensure at least one sysref edge
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clock::spin_us(1000); // ensure at least one sysref edge
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if read(ad9154_reg::SYNC_STATUS) & ad9154_reg::SYNC_LOCK == 0:
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return Err("no sync lock")
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write(ad9154_reg::XBAR_LN_0_1,
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@ -413,15 +414,15 @@ fn cfg() -> Result<(), &'static str> {
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jesd_enable(false);
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jesd_prbs(false);
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jesd_stpl(false);
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busywait_us(10000);
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clock::spin_us(10000);
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jesd_enable(true);
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dac_setup();
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jesd_enable(false);
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busywait_us(10000);
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clock::spin_us(10000);
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jesd_enable(true);
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monitor();
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while !jesd_ready() {}
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busywait_us(10000);
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clock::spin_us(10000);
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if read(ad9154_reg::CODEGRPSYNCFLG) != 0x0f {
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return Err("bad CODEGRPSYNCFLG")
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}
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@ -1,4 +1,4 @@
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use board::csr;
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use csr;
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const INIT: u64 = ::core::i64::MAX as u64;
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const FREQ: u64 = csr::CONFIG_CLOCK_FREQUENCY as u64;
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@ -7,6 +7,7 @@ include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/mem.rs"));
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include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/csr.rs"));
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pub mod spr;
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pub mod irq;
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pub mod clock;
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extern {
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pub fn flush_cpu_dcache();
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@ -58,7 +58,6 @@ pub extern fn panic_fmt(args: self::core::fmt::Arguments, file: &'static str, li
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}
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mod config;
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mod clock;
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mod rtio_mgt;
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mod mailbox;
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mod rpc_queue;
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@ -102,14 +101,14 @@ pub unsafe extern fn rust_main() {
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static mut LOG_BUFFER: [u8; 65536] = [0; 65536];
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BufferLogger::new(&mut LOG_BUFFER[..])
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.register(move || {
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clock::init();
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board::clock::init();
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info!("booting ARTIQ");
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info!("software version {}", GIT_COMMIT);
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info!("gateware version {}", board::ident(&mut [0; 64]));
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let t = clock::get_ms();
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let t = board::clock::get_ms();
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info!("press 'e' to erase startup and idle kernels...");
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while clock::get_ms() < t + 1000 {
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while board::clock::get_ms() < t + 1000 {
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if readchar_nonblock() != 0 && readchar() == b'e' as libc::c_char {
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config::remove("startup_kernel");
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config::remove("idle_kernel");
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@ -149,10 +148,10 @@ pub unsafe extern fn isr() {
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#[no_mangle]
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pub fn sys_now() -> u32 {
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clock::get_ms() as u32
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board::clock::get_ms() as u32
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}
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#[no_mangle]
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pub fn sys_jiffies() -> u32 {
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clock::get_ms() as u32
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board::clock::get_ms() as u32
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}
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@ -2,7 +2,7 @@ use core::{mem, ptr};
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use core::cell::{Cell, RefCell};
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use log::{self, Log, LogLevel, LogMetadata, LogRecord, LogLevelFilter};
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use log_buffer::LogBuffer;
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use clock;
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use board;
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pub struct BufferLogger {
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buffer: RefCell<LogBuffer<&'static mut [u8]>>,
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@ -70,13 +70,13 @@ impl Log for BufferLogger {
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use core::fmt::Write;
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writeln!(self.buffer.borrow_mut(),
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"[{:12}us] {:>5}({}): {}",
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clock::get_us(), record.level(), record.target(), record.args()).unwrap();
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board::clock::get_us(), record.level(), record.target(), record.args()).unwrap();
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// Printing to UART is really slow, so avoid doing that when we have an alternative
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// route to retrieve the debug messages.
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if self.trace_to_uart.get() || record.level() <= LogLevel::Info {
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println!("[{:12}us] {:>5}({}): {}",
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clock::get_us(), record.level(), record.target(), record.args());
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board::clock::get_us(), record.level(), record.target(), record.args());
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}
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}
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}
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@ -4,8 +4,7 @@ use sched::Scheduler;
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#[cfg(has_rtio_crg)]
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pub mod crg {
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use clock;
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use board::csr;
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use board::{clock, csr};
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pub fn init() {
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unsafe { csr::rtio_crg::pll_reset_write(0) }
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@ -6,7 +6,7 @@ use std::io::{Read, Write, Result, Error, ErrorKind};
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use fringe::OwnedStack;
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use fringe::generator::{Generator, Yielder, State as GeneratorState};
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use lwip;
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use clock;
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use board;
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use urc::Urc;
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#[derive(Debug)]
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@ -106,7 +106,7 @@ impl Scheduler {
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if self.threads.len() == 0 { return }
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let now = clock::get_ms();
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let now = board::clock::get_ms();
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let start_index = self.index;
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loop {
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@ -216,7 +216,7 @@ pub struct Waiter<'a>(&'a Yielder<WaitResult, WaitRequest, OwnedStack>);
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impl<'a> Waiter<'a> {
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pub fn sleep(&self, duration_ms: u64) -> Result<()> {
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let request = WaitRequest {
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timeout: Some(clock::get_ms() + duration_ms),
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timeout: Some(board::clock::get_ms() + duration_ms),
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event: None
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};
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@ -3,7 +3,7 @@ use std::{mem, str};
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use std::cell::RefCell;
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use std::io::{self, Read, Write, BufWriter};
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use std::btree_set::BTreeSet;
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use {config, rtio_mgt, clock, mailbox, rpc_queue, kernel};
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use {config, rtio_mgt, mailbox, rpc_queue, kernel};
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use logger::BufferLogger;
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use cache::Cache;
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use urc::Urc;
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@ -58,7 +58,7 @@ enum KernelState {
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struct Session<'a> {
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congress: &'a mut Congress,
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kernel_state: KernelState,
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watchdog_set: clock::WatchdogSet,
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watchdog_set: board::clock::WatchdogSet,
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log_buffer: String,
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interner: BTreeSet<String>
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}
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@ -68,7 +68,7 @@ impl<'a> Session<'a> {
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Session {
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congress: congress,
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kernel_state: KernelState::Absent,
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watchdog_set: clock::WatchdogSet::new(),
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watchdog_set: board::clock::WatchdogSet::new(),
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log_buffer: String::new(),
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interner: BTreeSet::new()
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}
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