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sayma_amc: more fighting with vivado timing analyzer

This commit is contained in:
Sebastien Bourdeauducq 2019-01-05 12:25:30 +08:00
parent 94cdad6c1d
commit 2100a8b1f1
1 changed files with 7 additions and 1 deletions
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8
artiq/gateware/targets/sayma_amc.py
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@ -326,13 +326,19 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
gth = self.drtio_transceiver.gths[0] gth = self.drtio_transceiver.gths[0]
platform.add_period_constraint(gth.txoutclk, rtio_clk_period/2) platform.add_period_constraint(gth.txoutclk, rtio_clk_period/2)
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
self.drtio_transceiver.cd_rtio.clk.attr.add("keep")
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.crg.cd_sys.clk,
gth.txoutclk, gth.rxoutclk) self.drtio_transceiver.cd_rtio.clk, gth.rxoutclk)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk)
for gth in self.drtio_transceiver.gths[1:]: for gth in self.drtio_transceiver.gths[1:]:
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.crg.cd_sys.clk, gth.rxoutclk) self.crg.cd_sys.clk, gth.rxoutclk)
platform.add_false_path_constraints(
self.drtio_transceiver.cd_rtio.clk, gth.rxoutclk)
platform.add_false_path_constraints(self.ad9154_crg.cd_jesd.clk,
self.drtio_transceiver.cd_rtio.clk)
rtio_channels = [] rtio_channels = []
for i in range(4): for i in range(4):