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drtio: add sat -> mst async notif packet

pull/2172/head
mwojcik 2023-12-06 17:23:04 +08:00 committed by Sébastien Bourdeauducq
parent 4956fac861
commit 1cc7398bc0
7 changed files with 42 additions and 3 deletions
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8
artiq/gateware/drtio/core.py
View File

@ -78,6 +78,7 @@ class DRTIOSatellite(Module):
self.reset = CSRStorage(reset=1)
self.reset_phy = CSRStorage(reset=1)
self.tsc_loaded = CSR()
self.async_messages_ready = CSR()
# master interface in the sys domain
self.cri = cri.Interface()
self.async_errors = Record(async_errors_layout)
@ -129,6 +130,9 @@ class DRTIOSatellite(Module):
link_layer_sync, interface=self.cri)
self.comb += self.rt_packet.reset.eq(self.cd_rio.rst)
self.sync += If(self.async_messages_ready.re, self.rt_packet.async_msg_stb.eq(1))
self.comb += self.async_messages_ready.w.eq(self.rt_packet.async_msg_ack)
self.comb += [
tsc.load.eq(self.rt_packet.tsc_load),
tsc.load_value.eq(self.rt_packet.tsc_load_value)
@ -136,14 +140,14 @@ class DRTIOSatellite(Module):
self.sync += [
If(self.tsc_loaded.re, self.tsc_loaded.w.eq(0)),
If(self.rt_packet.tsc_load, self.tsc_loaded.w.eq(1))
If(self.rt_packet.tsc_load, self.tsc_loaded.w.eq(1)),
]
self.submodules.rt_errors = rt_errors_satellite.RTErrorsSatellite(
self.rt_packet, tsc, self.async_errors)
def get_csrs(self):
return ([self.reset, self.reset_phy, self.tsc_loaded] +
return ([self.reset, self.reset_phy, self.tsc_loaded, self.async_messages_ready] +
self.link_layer.get_csrs() + self.link_stats.get_csrs() +
self.rt_errors.get_csrs())

6
artiq/gateware/drtio/rt_controller_master.py
View File

@ -17,6 +17,7 @@ class _CSRs(AutoCSR):
self.set_time = CSR()
self.underflow_margin = CSRStorage(16, reset=300)
self.async_messages_ready = CSR()
self.force_destination = CSRStorage()
self.destination = CSRStorage(8)
@ -60,6 +61,11 @@ class RTController(Module):
If(self.csrs.set_time.re, rt_packet.set_time_stb.eq(1))
]
self.sync += [
If(rt_packet.async_messages_ready, self.csrs.async_messages_ready.w.eq(1)),
If(self.csrs.async_messages_ready.re, self.csrs.async_messages_ready.w.eq(0))
]
# chan_sel forcing
chan_sel = Signal(24)
self.comb += chan_sel.eq(Mux(self.csrs.force_destination.storage,

7
artiq/gateware/drtio/rt_controller_repeater.py
View File

@ -14,6 +14,7 @@ class RTController(Module, AutoCSR):
self.command_missed_cmd = CSRStatus(2)
self.command_missed_chan_sel = CSRStatus(24)
self.buffer_space_timeout_dest = CSRStatus(8)
self.async_messages_ready = CSR()
self.sync += rt_packet.reset.eq(self.reset.storage)
@ -23,6 +24,12 @@ class RTController(Module, AutoCSR):
]
self.comb += self.set_time.w.eq(rt_packet.set_time_stb)
self.sync += [
If(rt_packet.async_messages_ready, self.async_messages_ready.w.eq(1)),
If(self.async_messages_ready.re, self.async_messages_ready.w.eq(0))
]
errors = [
(rt_packet.err_unknown_packet_type, "rtio_rx", None, None),
(rt_packet.err_packet_truncated, "rtio_rx", None, None),

7
artiq/gateware/drtio/rt_packet_master.py
View File

@ -61,6 +61,9 @@ class RTPacketMaster(Module):
# a set_time request pending
self.tsc_value = Signal(64)
# async aux messages interface, only received
self.async_messages_ready = Signal()
# rx errors
self.err_unknown_packet_type = Signal()
self.err_packet_truncated = Signal()
@ -283,12 +286,16 @@ class RTPacketMaster(Module):
echo_received_now = Signal()
self.sync.rtio_rx += self.echo_received_now.eq(echo_received_now)
async_messages_ready = Signal()
self.sync.rtio_rx += self.async_messages_ready.eq(async_messages_ready)
rx_fsm.act("INPUT",
If(rx_dp.frame_r,
rx_dp.packet_buffer_load.eq(1),
If(rx_dp.packet_last,
Case(rx_dp.packet_type, {
rx_plm.types["echo_reply"]: echo_received_now.eq(1),
rx_plm.types["async_messages_ready"]: async_messages_ready.eq(1),
rx_plm.types["buffer_space_reply"]: NextState("BUFFER_SPACE"),
rx_plm.types["read_reply"]: NextState("READ_REPLY"),
rx_plm.types["read_reply_noevent"]: NextState("READ_REPLY_NOEVENT"),

4
artiq/gateware/drtio/rt_packet_repeater.py
View File

@ -19,6 +19,7 @@ class RTPacketRepeater(Module):
# in rtio_rx domain
self.err_unknown_packet_type = Signal()
self.err_packet_truncated = Signal()
self.async_messages_ready = Signal()
# in rtio domain
self.err_command_missed = Signal()
@ -304,6 +305,7 @@ class RTPacketRepeater(Module):
rx_dp.packet_buffer_load.eq(1),
If(rx_dp.packet_last,
Case(rx_dp.packet_type, {
rx_plm.types["async_messages_ready"]: self.async_messages_ready.eq(1),
rx_plm.types["buffer_space_reply"]: NextState("BUFFER_SPACE"),
rx_plm.types["read_reply"]: NextState("READ_REPLY"),
rx_plm.types["read_reply_noevent"]: NextState("READ_REPLY_NOEVENT"),
@ -331,4 +333,4 @@ class RTPacketRepeater(Module):
read_not.eq(1),
read_no_event.eq(1),
NextState("INPUT")
)
)

12
artiq/gateware/drtio/rt_packet_satellite.py
View File

@ -19,6 +19,9 @@ class RTPacketSatellite(Module):
self.tsc_load = Signal()
self.tsc_load_value = Signal(64)
self.async_msg_stb = Signal()
self.async_msg_ack = Signal()
if interface is None:
interface = cri.Interface()
self.cri = interface
@ -78,6 +81,8 @@ class RTPacketSatellite(Module):
)
]
self.sync += If(self.async_msg_ack, self.async_msg_stb.eq(0))
# RX FSM
cri_read = Signal()
cri_buffer_space = Signal()
@ -197,6 +202,7 @@ class RTPacketSatellite(Module):
tx_fsm.act("IDLE",
If(echo_req, NextState("ECHO")),
If(self.async_msg_stb, NextState("ASYNC_MESSAGES_READY")),
If(buffer_space_req, NextState("BUFFER_SPACE")),
If(read_request_pending & ~self.cri.i_status[2],
NextState("READ"),
@ -210,6 +216,12 @@ class RTPacketSatellite(Module):
If(tx_dp.packet_last, NextState("IDLE"))
)
tx_fsm.act("ASYNC_MESSAGES_READY",
self.async_msg_ack.eq(1),
tx_dp.send("async_messages_ready"),
If(tx_dp.packet_last, NextState("IDLE"))
)
tx_fsm.act("BUFFER_SPACE",
buffer_space_ack.eq(1),
tx_dp.send("buffer_space_reply", space=buffer_space),

1
artiq/gateware/drtio/rt_serializer.py
View File

@ -69,6 +69,7 @@ def get_s2m_layouts(alignment):
plm.add_type("read_reply", ("timestamp", 64), ("data", 32))
plm.add_type("read_reply_noevent", ("overflow", 1)) # overflow=0→timeout
plm.add_type("async_messages_ready")
return plm