mirror of https://github.com/m-labs/artiq
241 lines
8.1 KiB
Python
241 lines
8.1 KiB
Python
"""Real-time controller for master"""
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from migen import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.misc import WaitTimer
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from misoc.interconnect.csr import *
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from artiq.gateware.rtio import cri
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class _CSRs(AutoCSR):
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def __init__(self):
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self.reset = CSRStorage()
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self.protocol_error = CSR(3)
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self.set_time = CSR()
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self.underflow_margin = CSRStorage(16, reset=300)
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self.async_messages_ready = CSR()
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self.force_destination = CSRStorage()
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self.destination = CSRStorage(8)
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self.o_get_buffer_space = CSR()
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self.o_dbg_buffer_space = CSRStatus(16)
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self.o_dbg_buffer_space_req_cnt = CSRStatus(32)
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self.o_wait = CSRStatus()
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class RTController(Module):
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def __init__(self, tsc, rt_packet):
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self.csrs = _CSRs()
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self.cri = cri.Interface()
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# protocol errors
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err_unknown_packet_type = Signal()
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err_packet_truncated = Signal()
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signal_buffer_space_timeout = Signal()
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err_buffer_space_timeout = Signal()
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self.sync += [
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If(self.csrs.protocol_error.re,
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If(self.csrs.protocol_error.r[0], err_unknown_packet_type.eq(0)),
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If(self.csrs.protocol_error.r[1], err_packet_truncated.eq(0)),
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If(self.csrs.protocol_error.r[2], err_buffer_space_timeout.eq(0))
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),
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If(rt_packet.err_unknown_packet_type, err_unknown_packet_type.eq(1)),
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If(rt_packet.err_packet_truncated, err_packet_truncated.eq(1)),
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If(signal_buffer_space_timeout, err_buffer_space_timeout.eq(1))
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]
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self.comb += self.csrs.protocol_error.w.eq(
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Cat(err_unknown_packet_type, err_packet_truncated, err_buffer_space_timeout))
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# TSC synchronization
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self.comb += [
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rt_packet.tsc_value.eq(tsc.coarse_ts),
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self.csrs.set_time.w.eq(rt_packet.set_time_stb)
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]
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self.sync += [
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If(rt_packet.set_time_ack, rt_packet.set_time_stb.eq(0)),
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If(self.csrs.set_time.re, rt_packet.set_time_stb.eq(1))
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]
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self.sync += [
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If(rt_packet.async_messages_ready, self.csrs.async_messages_ready.w.eq(1)),
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If(self.csrs.async_messages_ready.re, self.csrs.async_messages_ready.w.eq(0))
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]
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# chan_sel forcing
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chan_sel = Signal(24)
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self.comb += chan_sel.eq(Mux(self.csrs.force_destination.storage,
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self.csrs.destination.storage << 16,
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self.cri.chan_sel))
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# common packet fields
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rt_packet_buffer_request = Signal()
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rt_packet_read_request = Signal()
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self.comb += [
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rt_packet.sr_chan_sel.eq(chan_sel),
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rt_packet.sr_address.eq(self.cri.o_address),
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rt_packet.sr_data.eq(self.cri.o_data),
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If(rt_packet_read_request,
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rt_packet.sr_timestamp.eq(self.cri.i_timeout)
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).Else(
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rt_packet.sr_timestamp.eq(self.cri.o_timestamp)
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),
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If(rt_packet_buffer_request,
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rt_packet.sr_notwrite.eq(1),
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rt_packet.sr_address.eq(0)
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),
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If(rt_packet_read_request,
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rt_packet.sr_notwrite.eq(1),
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rt_packet.sr_address.eq(1)
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)
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]
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# output status
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o_status_wait = Signal()
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o_status_underflow = Signal()
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self.comb += [
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self.cri.o_status.eq(Cat(o_status_wait, o_status_underflow)),
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self.csrs.o_wait.status.eq(o_status_wait)
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]
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o_underflow_set = Signal()
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self.sync += [
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If(self.cri.cmd == cri.commands["write"],
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o_status_underflow.eq(0)
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),
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If(o_underflow_set, o_status_underflow.eq(1))
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]
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timeout_counter = WaitTimer(8191)
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self.submodules += timeout_counter
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cond_underflow = Signal()
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self.comb += cond_underflow.eq((self.cri.o_timestamp[tsc.glbl_fine_ts_width:]
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- self.csrs.underflow_margin.storage[tsc.glbl_fine_ts_width:]) < tsc.coarse_ts)
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# buffer space
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buffer_space = Memory(16, 256)
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buffer_space_port = buffer_space.get_port(write_capable=True)
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self.specials += buffer_space, buffer_space_port
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buffer_space_load = Signal()
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buffer_space_dec = Signal()
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self.comb += [
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buffer_space_port.adr.eq(chan_sel[16:]),
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buffer_space_port.we.eq(buffer_space_load | buffer_space_dec),
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If(buffer_space_load,
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buffer_space_port.dat_w.eq(rt_packet.buffer_space)
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).Else(
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buffer_space_port.dat_w.eq(buffer_space_port.dat_r - 1)
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)
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]
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# input status
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i_status_wait_event = Signal()
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i_status_overflow = Signal()
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i_status_wait_status = Signal()
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self.comb += self.cri.i_status.eq(Cat(
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i_status_wait_event, i_status_overflow, i_status_wait_status))
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load_read_reply = Signal()
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self.sync += [
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If(load_read_reply,
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i_status_wait_event.eq(0),
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i_status_overflow.eq(0),
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If(rt_packet.read_no_event,
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If(rt_packet.read_is_overflow,
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i_status_overflow.eq(1)
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).Else(
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i_status_wait_event.eq(1)
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)
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),
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self.cri.i_data.eq(rt_packet.read_data),
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self.cri.i_timestamp.eq(rt_packet.read_timestamp)
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)
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]
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# FSM
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fsm = FSM()
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self.submodules += fsm
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fsm.act("IDLE",
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If(self.cri.cmd == cri.commands["write"],
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If(cond_underflow,
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o_underflow_set.eq(1)
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).Else(
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NextState("WRITE")
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)
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),
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If(self.cri.cmd == cri.commands["read"], NextState("READ")),
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If(self.csrs.o_get_buffer_space.re, NextState("GET_BUFFER_SPACE"))
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)
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fsm.act("WRITE",
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o_status_wait.eq(1),
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rt_packet.sr_stb.eq(1),
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If(rt_packet.sr_ack,
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buffer_space_dec.eq(1),
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If(buffer_space_port.dat_r <= 1,
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NextState("GET_BUFFER_SPACE")
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).Else(
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NextState("IDLE")
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)
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)
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)
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fsm.act("GET_BUFFER_SPACE",
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o_status_wait.eq(1),
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rt_packet.buffer_space_not_ack.eq(1),
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rt_packet_buffer_request.eq(1),
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rt_packet.sr_stb.eq(1),
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If(rt_packet.sr_ack,
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NextState("GET_BUFFER_SPACE_REPLY")
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)
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)
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fsm.act("GET_BUFFER_SPACE_REPLY",
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o_status_wait.eq(1),
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buffer_space_load.eq(1),
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rt_packet.buffer_space_not_ack.eq(1),
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If(rt_packet.buffer_space_not,
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If(rt_packet.buffer_space != 0,
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NextState("IDLE")
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).Else(
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NextState("GET_BUFFER_SPACE")
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)
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),
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timeout_counter.wait.eq(1),
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If(timeout_counter.done,
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signal_buffer_space_timeout.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("READ",
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i_status_wait_status.eq(1),
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rt_packet.read_not_ack.eq(1),
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rt_packet_read_request.eq(1),
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rt_packet.sr_stb.eq(1),
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If(rt_packet.sr_ack,
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NextState("GET_READ_REPLY")
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)
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)
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fsm.act("GET_READ_REPLY",
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i_status_wait_status.eq(1),
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rt_packet.read_not_ack.eq(1),
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If(self.csrs.reset.storage | rt_packet.read_not,
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load_read_reply.eq(1),
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NextState("IDLE")
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)
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)
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# debug CSRs
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self.comb += self.csrs.o_dbg_buffer_space.status.eq(buffer_space_port.dat_r),
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self.sync += \
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If((rt_packet.sr_stb & rt_packet.sr_ack & rt_packet_buffer_request),
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self.csrs.o_dbg_buffer_space_req_cnt.status.eq(
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self.csrs.o_dbg_buffer_space_req_cnt.status + 1)
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)
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def get_csrs(self):
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return self.csrs.get_csrs()
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