M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

doc/core_device: update, add KC705 QC1 TTL table

This commit is contained in:
Sebastien Bourdeauducq 2015-08-18 16:04:27 +08:00
parent 2c15bd3e44
commit 178816243c
1 changed files with 23 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
doc/manual/core_device.rst
View File

@ -26,7 +26,25 @@ FPGA board ports
KC705 KC705
----- -----
The main target board for the ARTIQ core device is the KC705 development board from Xilinx. The main target board for the ARTIQ core device is the KC705 development board from Xilinx. It supports the NIST QC1 hardware via an adapter, and the NIST QC2 hardware (FMC).
With the QC1 hardware, the TTL lines are mapped as follows:
+--------------+------------+--------------+
| RTIO channel | TTL line | Capability |
+==============+============+==============+
| 0 | PMT0 | Input |
+--------------+------------+--------------+
| 1 | PMT1 | Input |
+--------------+------------+--------------+
| 2-16 | TTL0-14 | Output |
+--------------+------------+--------------+
| 17 | SMA_GPIO_N | Input+Output |
+--------------+------------+--------------+
| 18 | LED | Output |
+--------------+------------+--------------+
| 19 | TTL15 | Clock |
+--------------+------------+--------------+
Pipistrello Pipistrello
----------- -----------
@ -44,17 +62,15 @@ When plugged to an adapter, the NIST QC1 hardware can be used. The TTL lines are
+--------------+----------+------------+ +--------------+----------+------------+
| 2-16 | TTL0-14 | Output | | 2-16 | TTL0-14 | Output |
+--------------+----------+------------+ +--------------+----------+------------+
| 17 | TTL15 | Clock | | 17 | EXT_LED | Output |
+--------------+----------+------------+ +--------------+----------+------------+
| 18 | EXT_LED | Output | | 18 | USER_LED | Output |
+--------------+----------+------------+ +--------------+----------+------------+
| 19 | USER_LED | Output | | 19 | TTL15 | Clock |
+--------------+----------+------------+
| 20 | DDS | Output |
+--------------+----------+------------+ +--------------+----------+------------+
The input only limitation on channels 0 and 1 comes from the QC-DAQ adapter. When the adapter is not used (and physically unplugged from the Pipistrello board), the corresponding pins on the Pipistrello can be used as outputs. Do not configure these channels as outputs when the adapter is plugged, as this would cause electrical contention. The input only limitation on channels 0 and 1 comes from the QC-DAQ adapter. When the adapter is not used (and physically unplugged from the Pipistrello board), the corresponding pins on the Pipistrello can be used as outputs. Do not configure these channels as outputs when the adapter is plugged, as this would cause electrical contention.
The board can accept an external RTIO clock connected to PMT2. If the DDS box The board can accept an external RTIO clock connected to PMT2. If the DDS box
does not drive the PMT2 pair, use XTRIG and patch the XTRIG transciever output does not drive the PMT2 pair, use XTRIG and patch the XTRIG transceiver output
on the adapter board onto C:15 disconnecting PMT2. on the adapter board onto C:15 disconnecting PMT2.