mirror of https://github.com/m-labs/artiq.git
gateware/rtio/analyzer: fix event ordering
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@ -214,7 +214,7 @@ class Analyzer(Module, AutoCSR):
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self.submodules.message_encoder = MessageEncoder(rtio_core)
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self.submodules.converter = stream.Converter(
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[("data", 256)], [("data", dw)])
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[("data", 256)], [("data", dw)], reverse=True)
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self.submodules.fifo = stream.SyncFIFO(
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[("data", dw)], fifo_depth, True)
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self.submodules.dma = DMAWriter(membus)
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