2
0
mirror of https://github.com/m-labs/artiq.git synced 2024-12-26 11:48:27 +08:00

feature gate txenable with has_drtio_eem

This commit is contained in:
occheung 2024-10-24 12:35:10 +08:00
parent a643da2c5e
commit 1583debfe7

View File

@ -641,7 +641,7 @@ fn process_aux_packet(dmamgr: &mut DmaManager, analyzer: &mut Analyzer, kernelmg
drtioaux::Packet::CoreMgmtDropLinkAck { destination: _destination } => {
forward!(router, _routing_table, _destination, *rank, *self_destination, _repeaters, &packet);
#[cfg(not(soc_platform = "efc"))]
#[cfg(not(has_drtio_eem))]
unsafe {
csr::gt_drtio::txenable_write(0);
}